SBOS513F August   2010  – December 2016 OPA2320 , OPA320

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA320 and OPA320S
    5. 6.5 Thermal Information: OPA2320
    6. 6.6 Thermal Information: OPA2320S
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Voltage
      2. 7.3.2  Input and ESD Protection
      3. 7.3.3  Rail-to-Rail Input
      4. 7.3.4  Phase Reversal
      5. 7.3.5  Feedback Capacitor Improves Response
      6. 7.3.6  EMI Susceptibility and Input Filtering
      7. 7.3.7  Output Impedance
      8. 7.3.8  Capacitive Load and Stability
      9. 7.3.9  Overload Recovery Time
      10. 7.3.10 Shutdown Function
      11. 7.3.11 Leadless SON Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transimpedance Amplifier
      2. 8.1.2 Optimizing the Transimpedance Circuit
      3. 8.1.3 High-Impedance Sensor Interface
      4. 8.1.4 Driving ADC'S
      5. 8.1.5 Active Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ (Free Software Download)
        2. 11.1.1.2 DIP Adapter EVM
        3. 11.1.1.3 Universal Op Amp EVM
        4. 11.1.1.4 TI Precision Designs
        5. 11.1.1.5 WEBENCH® Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resource
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply, VS = (V+) – (V–) 6 V
Signal input pin(2) (V–) – 0.5 (V+) + 0.5
Current Signal input pin(2) –10 10 mA
Output short-circuit current(3) Continuous
Temperature Operating range, TA –40 150 °C
Junction, TJ 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS Specified voltage 1.8 5.5 V
TA Specified temperature –40 125 °C

6.4 Thermal Information: OPA320 and OPA320S

THERMAL METRIC OPA320 OPA320S UNIT
DBV (SOT-23) DBV (SOT-23)
5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance(1) 219.3 177.5 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 107.5 108.9 °C/W
RθJB Junction-to-board thermal resistance 57.5 27.4 °C/W
ψJT Junction-to-top characterization parameter 7.4 13.3 °C/W
ψJB Junction-to-board characterization parameter 56.9 26.9 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance — — °C/W
(1) For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal Metrics.

6.5 Thermal Information: OPA2320

THERMAL METRIC(1) OPA2320 UNIT
D (SOIC) DGK (VSSOP) DRG (SON)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 122.6 174.8 50.6 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 67.1 43.9 54.9 °C/W
RθJB Junction-to-board thermal resistance 64 95 25.2 °C/W
ψJT Junction-to-top characterization parameter 13.2 2 0.6 °C/W
ψJB Junction-to-board characterization parameter 63.4 93.5 25.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance — — 5.7 °C/W
(1) For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal Metrics.

6.6 Thermal Information: OPA2320S

THERMAL METRIC(1) OPA2320S UNIT
DGS (VSSOP)
10 PINS
RθJA Junction-to-ambient thermal resistance 171.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 43 °C/W
RθJB Junction-to-board thermal resistance 91.4 °C/W
ψJT Junction-to-top characterization parameter 1.9 °C/W
ψJB Junction-to-board characterization parameter 89.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.7 Electrical Characteristics

At VS = 1.8 V to 5.5 V or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and
SHDN x = VS+ (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 40 150 µV
dVOS/dT Input offset voltage
vs temperature		 VS = 5.5 V, TA = –40°C to 125°C 1.5 5 µV/°C
PSR Input offset voltage
vs power supply		 VS = 1.8 V to 5.5 V, TA = 25°C 5 20 µV/V
VS = 1.8 V to 5.5 V, TA = –40°C to 125°C 15
Channel separation 1 kHz 130 dB
INPUT VOLTAGE
VCM Common-mode voltage (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = 25°C 100 114 dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = –40°C to 125°C 96
INPUT BIAS CURRENT
IB Input bias current TA = 25°C ±0.2 ±0.9 pA
TA = –40°C to 85°C ±50
TA = –40°C to 125°C OPA2320 and OPA2320S ±400
OPA320 and OPA320S ±600
IOS Input offset current TA = 25°C ±0.2 ±0.9 pA
TA = –40°C to 85°C ±50
TA = –40°C to 125°C ±400
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 2.8 µVPP
en Input voltage noise density f = 1 kHz 8.5 nV/√Hz
f = 10 kHz 7
in Input current noise density f = 1 kHz 0.6 fA/√Hz
INPUT CAPACITANCE
Differential 5 pF
Common mode 4 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain 0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ, TA = 25°C 114 132 dB
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ, TA = –40°C to 125°C 100 130
0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ, TA = 25°C 108 123
0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ, TA = –40°C to 125°C 96 130
PM Phase margin VS = 5 V, CL = 50 pF 47 °
FREQUENCY RESPONSE, VS = 5 V, CL = 50 pF
GBP Gain bandwidth product Unity gain 20 MHz
SR Slew rate G = +1 10 V/µs
tS Settling time to 0.1%, 2-V step, G = +1 0.25 µs
to 0.01%, 2-V step, G = +1 0.32
to 0.0015%, 2-V step, G = +1(1) 0.5
Overload recovery time VIN × G > VS 100 ns
THD+N Total harmonic distortion + noise(2) VO = 4 VPP, G = 1, f = 10 kHz, RL = 10 kΩ 0.0005%
VO = 2 VPP, G = 1, f = 10 kHz, RL = 600 Ω 0.0011%
OUTPUT
VO Voltage output swing from both rails RL = 10 kΩ, TA = 25°C 10 20 mV
RL = 2 kΩ, TA = 25°C 25 35
RL = 10 kΩ, TA = –40°C to 125°C 30
RL = 2 kΩ, TA = –40°C to 125°C 45
ISC Short-circuit current VS = 5.5 V ±65 mA
CL Capacitive load drive See Typical Characteristics
RO Open-loop output resistance IO = 0 mA, f = 1 MHz 90 Ω
SHUTDOWN (3)
IQSD Quiescent current per amplifier All amplifiers disabled, SHDN = V– 0.1 0.5 µA
OPA2320S only, SHDN A = VS–, SHDN B = VS+ 1.6 mA
OPA2320S only, SHDN A = VS+, SHDN B = VS– 1.6
VIH High-level input voltage Amplifier enabled, VS– + 0.7 [(VS+) + |VS–|] 0.7 × VS+ 5.5 V
VIL Low-level input voltage Amplifier disabled, VS– + 0.3 [(VS+) + |VS–|] 0.3 × VS+ V
tON Amplifier enable time(4) G = 1, VOUT = 0.1 × VS/2, full shutdown(5) 20 µs
OPA2320S only, partial shutdown(5) 6
tOFF Amplifier disable time(4) G = 1, VOUT = 0.1 × VS/2 3 µs
SHDN pin input bias current (per pin) VIH = 5 V 0.13 µA
VIL = 0 V 0.04
POWER SUPPLY
VS Specified voltage 1.8 5.5 V
IQ Quiescent current per amplifier,
OPA320 and OPA320S		 IO = 0 mA, VS = 5.5 V, TA = 25°C 1.5 1.75 mA
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C 1.85
Quiescent current per amplifier,
OPA2320 and OPA2320S		 IO = 0 mA, VS = 5.5 V, TA = 25°C 1.45 1.6 mA
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C 1.7
Power-on time V+ = 0 V to 5 V, to 90% IQ level 28 µs
(1) Based on simulation.
(2) Third-order filter; bandwidth = 80 kHz at –3 dB.
(3) Specified by design and characterization; not production tested.
(4) Disable time (tOFF) and enable time (tON) are defined as the time between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(5) Full shutdown refers to the dual OPA2320S having both A and B channels disabled (SHDN A = SHDN B = VS–). For partial shutdown, only one SHDN pin is exercised; in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.

6.8 Typical Characteristics

At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted).
OPA320 OPA2320 OPA320S OPA2320S tc_histo_voff_bos513.gif
Figure 1. Offset Voltage Production Distribution
OPA320 OPA2320 OPA320S OPA2320S tc_vo-vcm_bos513.gif
Figure 3. Offset Voltage vs Common-Mode Voltage
OPA320 OPA2320 OPA320S OPA2320S tc_oloop_g-tmp_bos513.gif
Figure 5. Open-Loop Gain vs Temperature
OPA320 OPA2320 OPA320S OPA2320S tc_ibc-vs_bos513.gif
Figure 7. Input Bias Current vs Supply Voltage
OPA320 OPA2320 OPA320S OPA2320S tc_histo_ibias_bos513.gif
Figure 9. Input Bias Current Distribution
OPA320 OPA2320 OPA320S OPA2320S tc_cmrr_psrr-frq_bos513.gif
Figure 11. CMRR and PSRR vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_noise_density_bos513.gif
Figure 13. Input Voltage Noise Spectral Density
vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_cloop-frq_18v_bos513.gif
Figure 15. Closed-Loop Gain vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_max_vo-frq_bos513.gif
Figure 17. Maximum Output Voltage vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_oloop_imp-frq_bos513.gif
Figure 19. Open-Loop Output Impedance vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_thdn-amp_bos513.gif
Figure 21. THD+N vs Amplitude
OPA320 OPA2320 OPA320S OPA2320S tc_thdn-frq_4vin_bos513.gif
Figure 23. THD+N vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_sr-vs_bos513.gif
Figure 25. Slew Rate vs Supply Voltage
OPA320 OPA2320 OPA320S OPA2320S tc_sm_step_neg_bos513.gif
Figure 27. Small-Signal Step Response
OPA320 OPA2320 OPA320S OPA2320S C001_SBOS600.png
Figure 29. Enable Start-Up
OPA320 OPA2320 OPA320S OPA2320S C003_SBOS600.png
Figure 31. Enable Shutdown
OPA320 OPA2320 OPA320S OPA2320S tc_histo_voff_drift_bos513.gif
Figure 2. Offset Voltage Drift Distribution
OPA320 OPA2320 OPA320S OPA2320S tc_oloop_g_ph-frq_bos513.gif
Figure 4. Open-Loop Gain/Phase vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_iq-vs_bos513.gif
Figure 6. Quiescent Current vs Supply Voltage
OPA320 OPA2320 OPA320S OPA2320S tc_ibc-vcm_bos513.gif
Figure 8. Input Bias Current vs Common-Mode Voltage
OPA320 OPA2320 OPA320S OPA2320S tc_ibc-tmp_bos513.gif
Figure 10. Input Bias Current vs Temperature
OPA320 OPA2320 OPA320S OPA2320S tc_cmrr_psrr-tmp_bos513.gif
Figure 12. CMRR and PSRR vs Temperature
OPA320 OPA2320 OPA320S OPA2320S tc_vin_noise_bos513.gif
Figure 14. 0.1-Hz to 10-Hz Input Voltage Noise
OPA320 OPA2320 OPA320S OPA2320S tc_cloop-frq_55v_bos513.gif
Figure 16. Closed-Loop Gain vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_vo-io_bos538.gif
Figure 18. Output Voltage Swing vs Output Current
(8-Pin VSSOP)
OPA320 OPA2320 OPA320S OPA2320S tc_oshoot-cl_bos513.gif
Figure 20. Small-Signal Overshoot vs Load Capacitance
OPA320 OPA2320 OPA320S OPA2320S tc_thdn-frq_2vin_bos513.gif
Figure 22. THD+N vs Frequency
OPA320 OPA2320 OPA320S OPA2320S tc_ch_sep-frq_bos513.gif
Figure 24. Channel Separation vs Frequency
(for Dual Versions)
OPA320 OPA2320 OPA320S OPA2320S tc_sm_step_pos_bos513.gif
Figure 26. Small-Signal Step Response
OPA320 OPA2320 OPA320S OPA2320S tc_lg_step_resp_bos513.gif
Figure 28. Large-Signal Step Response vs Time
OPA320 OPA2320 OPA320S OPA2320S C002_SBOS600.png
Figure 30. Enable Start-Up
OPA320 OPA2320 OPA320S OPA2320S C004_SBOS600.png
Figure 32. Enable Shutdown