Refer to the PDF data sheet for device specific package drawings
The OPA330 series of CMOS operational amplifiers offer precision performance at a very competitive price. These devices are members of the Zero-Drift family of amplifiers which use a proprietary auto-calibration technique to simultaneously provide low offset voltage (50-μV maximum) and near-zero drift over time and temperature at only 35 μA (maximum) of quiescent current. The OPA330 family features rail-to-rail input and output in addition to near-flat 1/f noise, making this amplifier ideal for many applications and much easier to design into a system. These devices are optimized for low-voltage operation as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V).
The OPA330 (single version) is available in the 5-pin DSBGA, 5-pin SC70, 5-pin SOT-23, and 8-pin SOIC packages. The OPA2330 (dual version) is offered in 3 mm × 3 mm, 8-pin SON, 8-pin VSSOP, and 8-pin SOIC packages. The OPA4330 is offered in the standard 14-pin SOIC and 14-pin TSSOP packages, as well as in the space-saving 14-pin VQFN package. All versions are specified for operation from –40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA330 | SOIC (8) | 4.90 mm × 3.91 mm |
SOT (5) | 2.90 mm × 1.60 mm | |
SC70 (5) | 2.00 mm × 1.25 mm | |
DSBGA (5) | 0.00 mm × 0.00 mm | |
OPA2330 | SOIC (8) | 4.90 mm × 3.91 mm |
VSSOP (8) | 3.00 mm × 3.00 mm | |
SON (8) | 3.00 mm × 3.00 mm | |
OPA4330 | SOIC (14) | 8.65 mm × 3.91 mm |
TSSOP (14) | 5.00 mm × 4.40 mm | |
VQFN (14) | 3.50 mm × 3.50 mm |
Changes from F Revision (June 2016) to G Revision
Changes from E Revision (February 2011) to F Revision
Changes from D Revision (June 2010) to E Revision
Changes from C Revision (October 2009) to D Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC, VSSOP |
SON | ||
–IN A | 2 | 2 | I | Negative (inverting) input signal, channel A |
+IN A | 3 | 3 | I | Positive (noninverting) input signal, channel A |
–IN B | 6 | 6 | I | Negative (inverting) input signal, channel B |
+IN B | 5 | 5 | I | Positive (noninverting) input signal, channel B |
OUT A | 1 | 1 | O | Output channel A |
OUT B | 7 | 7 | O | Output channel B |
V– | 4 | 4 | — | Negative (lowest) power supply |
V+ | 8 | 8 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | SOIC | TSSOP | VQFN | ||
–IN A | 2 | 2 | 2 | I | Negative (inverting) input signal, channel A |
+IN A | 3 | 3 | 3 | I | Positive (noninverting) input signal, channel A |
–IN B | 6 | 6 | 6 | I | Negative (inverting) input signal, channel B |
+IN B | 5 | 5 | 5 | I | Positive (noninverting) input signal, channel B |
–IN C | 9 | 9 | 9 | I | Negative (inverting) input signal, channel C |
+IN C | 10 | 10 | 10 | I | Positive (noninverting) input signal, channel C |
–IN D | 13 | 13 | 13 | I | Negative (inverting) input signal, channel D |
+IN D | 12 | 12 | 12 | I | Positive (noninverting) input signal, channel D |
OUT A | 1 | 1 | 1 | O | Output channel A |
OUT B | 7 | 7 | 7 | O | Output channel B |
OUT C | 8 | 8 | 8 | O | Output channel C |
OUT D | 14 | 14 | 14 | O | Output channel D |
V– | 11 | 11 | 11 | — | Negative (lowest) power supply |
V+ | 4 | 4 | 4 | — | Positive (highest) power supply |