The OPAx375 family includes single (OPA375), dual (OPA2375) and quad-channel (OPA2375) general-purpose CMOS operation amplifiers (op amp) that provide an extremely low noise figure of 3.5 nV/√Hz, a low offset of 500 µV (maximum) and a wide bandwidth of 10 MHz. The low noise and wide bandwidth make the OPAx375 family attractive for a variety of precision applications that require a good balance between cost and performance. Additionally, the input bias current of the OPAx375 supports applications with high source impedance.
The robust design of the OPAx375 family provides ease-of-use to the circuit designer due to the unity-gain stability, integrated RFI/EMI rejection filter, no phase reversal in overdrive conditions, and high electrostatic discharge (ESD) protection (2-kV HBM). Additionally, the resistive open-loop output impedance allows for easy stabilization with much higher capacitive loads.
This op amp is optimized for low-voltage operation as low as 2.25 V (±1.125 V) for the OPA375 and 1.7 V (±0.85 V) for the OPA2375 and OPA4375. All of the devices operate up to 5.5 V (±2.75 V), and are specified over the temperature range of –40°C to 125°C.
The single-channel OPA375 is available in a small-size SC70-5 package. The dual-channel OPA2375 is available in multiple package options including a tiny 1.5 mm × 2.0 mm X2QFN package.
PART NUMBER(1) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA375 | SC70 (5) | 1.25 mm × 2.00 mm |
OPA2375 | SOIC (8) | 3.91 mm × 4.90 mm |
TSSOP (8) | 3.00 mm × 4.40 mm | |
VSSOP (8) | 3.00 mm × 3.00 mm | |
SOT-23 (8) | 1.60 mm × 2.90 mm | |
WSON (8) | 2.00 mm × 2.00 mm | |
X2QFN (10) | 1.50 mm × 2.00 mm |
Changes from Revision D (February 2021) to Revision E (August 2021)
Changes from Revision C (June 2020) to Revision D (February 2021)
Changes from Revision B (January 2020) to Revision C (June 2020)
Changes from Revision A (January 2019) to Revision B (January 2020)
Changes from Revision * (November 2017) to Revision A (January 2019)
DEVICE | NO. OF CHANNELS |
PACKAGE LEADS | ||||||
---|---|---|---|---|---|---|---|---|
SOIC D |
SC-70 DCK |
VSSOP DGK |
WSON DSG |
TSSOP PW |
SOT-23 DDF |
X2QFN RUG |
||
OPA375 | 1 | — | 5 | — | — | — | — | — |
OPA2375 | 2 | 8 | — | 8 | 8 | 8 | 8 | — |
— | — | — | — | — | — | 10 |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
+IN | 1 | I | Noninverting input |
–IN | 3 | I | Inverting input |
OUT | 4 | O | Output |
V+ | 5 | — | Positive (highest) supply |
V– | 2 | — | Negative (lowest) supply or ground (for single-supply operation) |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN1– | 2 | I | Inverting input, channel 1 |
IN1+ | 3 | I | Noninverting input, channel 1 |
IN2– | 6 | I | Inverting input, channel 2 |
IN2+ | 5 | I | Noninverting input, channel 2 |
OUT1 | 1 | O | Output, channel 1 |
OUT2 | 7 | O | Output, channel 2 |
V– | 4 | — | Negative (lowest) supply or ground (for single-supply operation) |
V+ | 8 | — | Positive (highest) supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN1– | 9 | I | Inverting input, channel 1 |
IN1+ | 10 | I | Noninverting input, channel 1 |
IN2– | 5 | I | Inverting input, channel 2 |
IN2+ | 4 | I | Noninverting input, channel 2 |
OUT1 | 8 | O | Output, channel 1 |
OUT2 | 6 | O | Output, channel 2 |
SHDN1 | 2 | I | Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Section 8.3.7 for more information. |
SHDN2 | 3 | I | Shutdown: low = amp disabled, high = amp enabled. Channel 2. See Section 8.3.7 for more information. |
V– | 1 | I or — | Negative (lowest) supply or ground (for single-supply operation) |
V+ | 7 | I | Positive (highest) supply |