SBOS984 Data sheet

SBOS984G November 2020 – September 2023 OPA2387 , OPA387 , OPA4387

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

D|8
- MSOI002K
DSG|8
- MPDS308C
DGK|8
- MPDS028E

Thermal pad, mechanical data (Package|Pins)

DSG|8
- QFND141I

Orderable Information

6.8 Typical Characteristics

at T_A = 25°C, V_S = ±2.75 V, V_CM = V_S / 2, R_LOAD = 10 kΩ connected to V_S / 2, and C_L = 50 pF (unless otherwise noted)

V_S = 5.5 V, T_A = 25°C

Figure 6-1 Offset Voltage Distribution

V_S = 5.5 V, T_A = 125°C

Figure 6-3 Offset Voltage Distribution

Figure 6-5 Offset Voltage vs Temperature

Figure 6-7 Offset Voltage vs Supply Voltage

Figure 6-9 Open-Loop Gain vs Temperature

Figure 6-11 Input Bias Current vs Common-Mode Voltage

Figure 6-13 PSRR and CMRR vs Frequency

Figure 6-15 Input Voltage Noise Spectral Density vs Frequency

V_S = 5.5 V, V_OUT = 3 V_RMS, BW = 80 kHz

Figure 6-17 THD+N Ratio vs Frequency

Figure 6-19 Quiescent Current vs Supply Voltage

Figure 6-21 Open-Loop Output Impedance vs Frequency

G = +1, 10 mV step

Figure 6-23 Small-Signal Overshoot vs Capacitive Load

Figure 6-25 No Phase Reversal

G = +1

Figure 6-27 Small-Signal Step Response

0.01% settling = ±100 µV

Figure 6-29 Settling Time

V_S = 5.5 V, T_A = –40°C

Figure 6-2 Offset Voltage Distribution

V_S = 5.5 V

Figure 6-4 Offset Voltage Drift Distribution

Figure 6-6 Offset Voltage vs Common-Mode Voltage

Figure 6-8 Open-Loop Gain and Phase vs Frequency

Figure 6-10 Closed-Loop Gain vs Frequency

Figure 6-12 CMRR vs Temperature

Figure 6-14 0.1-Hz to 10-Hz Noise

Figure 6-16 Channel-to-Channel Crosstalk

V_S = 5.5 V, f = 1 kHz, BW = 80 kHz

Figure 6-18 THD+N vs Output Amplitude

Figure 6-20 Quiescent Current vs Temperature

G = –1, 10 mV step

Figure 6-22 Small-Signal Overshoot vs Capacitive Load

G = +1

Figure 6-24 Phase Margin vs Capacitive Load

G = –1

Figure 6-26 Overload Recovery

4-V step

Figure 6-28 Large-Signal Step Response