SBOS382H may   2008  – june 2023 OPA2673

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Family Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Full Bias and Offline Mode VS = ±6 V
    6. 7.6  Electrical Characteristics: 75% Bias Mode VS = ±6 V
    7. 7.7  Electrical Characteristics: 50% Bias Mode VS = ±6 V
    8. 7.8  Typical Characteristics: VS = ±6 V, Full Bias
    9. 7.9  Typical Characteristics: VS = ±6 V Differential, Full Bias
    10. 7.10 Typical Characteristics: VS = ±6 V, 75% Bias
    11. 7.11 Typical Characteristics: VS = ±6 V, 50% Bias
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Suggestions
        1. 8.3.1.1 Setting Resistor Values to Optimize Bandwidth
        2. 8.3.1.2 Output Current and Voltage
        3. 8.3.1.3 Driving Capacitive Loads
        4. 8.3.1.4 Line Driver Headroom Model
        5. 8.3.1.5 Noise Performance
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High-Speed Active Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 PLC Line Driver
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Thermal Analysis
      2. 9.3.2 Input and ESD Protection
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 TINA-TI™ Simulation Software (Free Download)
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1.3 Driving Capacitive Loads

One of the most demanding and yet very common load conditions for an op amp is capacitive loading. The capacitive load is often the input of an analog-to-digital converter (ADC), including additional external capacitance that can be recommended to improve the ADC linearity. A high-speed, high-open-loop gain amplifier, such as the OPA2673, can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin.

When the primary considerations are frequency-response flatness, pulse-response fidelity, and distortion, the simplest and most effective solution is to isolate the capacitive load (CL) from the feedback loop by inserting a series isolation resistor (RISO) between the amplifier output and the capacitive load. Figure 8-6 shows this configuration. This approach does not eliminate the pole from the loop response, but rather shifts the pole and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. Figure 8-7 shows the Recommended RISO vs CL, and Figure 8-8 shows the resulting frequency response with the optimized RISO value.

GUID-20211027-SS0I-1LSP-S1C4-0ZXMVVHDF8RK-low.svg Figure 8-6 Driving a Large Capacitive Load Using an Output Series Isolation Resistor
GUID-20211108-SS0I-MZQJ-1F1G-RVPHX01D0V7D-low.svg
Figure 8-7 Recommended RISO vs Capacitive Load
GUID-20211026-SS0I-RX2V-KW5F-RSRJXFSMSN55-low.svg
Figure 8-8 Frequency Response vs Capacitive Load