SBOSAA5C april   2022  – may 2023 OPA2675

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Family Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Full Bias and Offline Mode VS = ±6 V
    6. 7.6  Electrical Characteristics: 75% Bias Mode VS = ±6 V
    7. 7.7  Electrical Characteristics: 50% Bias Mode VS = ±6 V
    8. 7.8  Electrical Characteristics: DIfferential Output  VS = 12 V
    9. 7.9  Electrical Characteristics: VS = 5 V
    10. 7.10 Typical Characteristics: VS = ±6 V, Full Bias
    11. 7.11 Typical Characteristics: VS = ±6 V Differential, Full Bias
    12. 7.12 Typical Characteristics: VS = ±6 V, 75% Bias
    13. 7.13 Typical Characteristics: VS = ±6 V, 50% Bias
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Suggestions
        1. 8.3.1.1 Setting Resistor Values to Optimize Bandwidth
        2. 8.3.1.2 Output Current and Voltage
        3. 8.3.1.3 Driving Capacitive Loads
        4. 8.3.1.4 Line Driver Headroom Model
        5. 8.3.1.5 Noise Performance
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High-Speed Active Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Thermal Analysis
      2. 9.3.2 Input and ESD Protection
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 TINA-TI™ Simulation Software (Free Download)
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Achieving optimum performance with a high-frequency amplifier such as the OPA2675 requires careful attention to board layout parasitic and external component types.

a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input, parasitic capacitance can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, open a window around the signal I/O pins in all of the ground and power planes around those pins. Otherwise, make sure that ground and power planes are unbroken elsewhere on the board.

b) Minimize the distance (< 0.25 inches or 6.35 0 mm) from the power-supply pins to high-frequency, 0.1‑µF decoupling capacitors. Always decouple the power-supply connections (on pins 7 and 14 for a VQFN package) with low-ESR capacitors. Do not have the ground and power-plane layout in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor connected across the two power supplies (for bipolar operation) improves second-harmonic distortion performance.

c) Careful selection and placement of external components preserve the high-frequency performance of the OPA2675. Use very low reactance resistors. Surface-mount resistors, metal film, and carbon-composition-based axially-leaded resistors can provide good high-frequency performance. Keep the leads and PCB trace length as short as possible. Although the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins.

d) The frequency response is primarily determined by the feedback resistor value as described previously. Increasing the value reduces the bandwidth, whereas decreasing the value gives a more peaked frequency response. The 402‑Ω feedback resistor used in the Typical Characteristics at a gain of +4 V/V on ±6‑V supplies is a good starting point for design. Note that a current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. Use a 511‑Ω feedback resistor, rather than a direct short, for the unity-gain follower application.

e) Connections to other wideband devices on the board can be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Use relatively wide traces (50 mils to 100 mils, or 1.27 mm to 2.54 mm), preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of Figure 8-7. Low-parasitic capacitive loads (< 5 pF) may not need an RISO because the OPA2675 is nominally compensated to operate with a 2‑pF parasitic load.

If a long trace is required, and the 6‑dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched-impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques).

The high output voltage and current capability of the OPA2675 allows multiple destination devices to be handled as separate transmission lines, each with respective series and shunt terminations. If the 6‑dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only.