SBOS789C August   2017  – February 2020 OPA2810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Multichannel Sensor Interface
      2.      Harmonic Distortion vs Frequency
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: 10 V
    6. 7.6  Electrical Characteristics: 24 V
    7. 7.7  Electrical Characteristics: 5 V
    8. 7.8  Typical Characteristics: VS = 10 V
    9. 7.9  Typical Characteristics: VS = 24 V
    10. 7.10 Typical Characteristics: VS = 5 V
    11. 7.11 Typical Characteristics: ±2.375 V to ±12 V Split Supply
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OPA2810 Architecture
      2. 8.3.2 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
      2. 8.4.2 Single-Supply Operation (4.75 V to 27 V)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Selection of Feedback Resistors
      2. 9.1.2 Noise Analysis and the Effect of Resistor Elements on Total Noise
    2. 9.2 Typical Applications
      1. 9.2.1 Transimpedance Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Multichannel Sensor Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Electrical Characteristics: 5 V

Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, VCM = 1.25 V, RL = 1 kΩ, and output is biased to midsupply(5).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Test Level(1)
AC PERFORMANCE
SSBW Small-signal bandwidth G = 1, Vo = 20 mVPP, RF = 0 Ω 74 MHz C
G = 1, Vo = 20 mVPP, RF= 0 Ω,
CL= 33 pF		 103 MHz C
G = –1, Vo = 20 mVPP 51 MHz C
G = 2, Vo = 20 mVPP 49 MHz C
G = 5, Vo = 20 mVPP 15 MHz C
LSBW Large-signal bandwidth G = 2 Vo = 2 VPP 33 MHz C
GBWP Gain-bandwidth product G = 11, Vo = 20 mVPP 70 MHz C
Bandwdith for 0.1dB flatness G = 2, Vo = 20 mVPP 11 MHz C
SR Slew rate (20%-80%)(4) G = 2, Vo = –1-V to 1-V step 119 V/µs C
G = 2, Vo = –2-V to 2-V step, 
VS = ±2.5 V		 88 V/µs C
Rise time Vo = 200-mV step 4 ns C
Fall time Vo = 200-mV step 5 ns C
Settling time to 0.1% G = 2, Vo = –2-V to 0-V step, 
VS = ±2.5 V		 108 ns C
Settling time to 0.001% G = 2, Vo = –2-V to 0-V step, 
VS = ±2.5 V		 197 ns C
Overshoot/undershoot G = 1, Vo = 200 mVPP 10/11 % C
G = 1, Vo = –1.25-V to 0.75-V step 1/7 % C
Input overdrive recovery G = 1, (VS– – 0.5 V) to (VS+ + 0.5 V) input, VS = ±2.5 V (see Figure 39) 71 ns C
Output overdrive recovery G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V) input, VS = ±2.5 V (see Figure 40) 91 ns C
HD2 Second-order harmonic distortion f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –102 dBc C
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –85 dBc C
HD3 Third-order harmonic distortion f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –113 dBc C
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –97 dBc C
en Input-referred voltage noise f = 500 kHz, latband 6 nV/√Hz C
f = 0.1-10 Hz integrated 0.42 µVrms C
ei Input-referred current noise f = 10 kHz 5 fA/√Hz C
zO Close-loop output impedance f = 100 kHz 0.007 Ω C
DC PERFORMANCE
AOL Open-loop voltage gain f = DC, Vo = 1.25 V to 3.25 V 104 118 dB A
TA = –40°C to +125°C 104 dB B
VOS Input offset voltage TA = 25°C, no-load 0.1 1.5 mV A
TA = –40°C to +85°C 2.4 mV B
TA = –40°C to +125°C 2.8 mV B
Input offset voltage drift TA = 25°C, no-load 1.5 µV/°C B
TA = –40°C to +125°C 13 µV/°C B
Input bias current TA = 25°C 2 20 pA A
TA = –40°C to +85°C(6) 20 50 pA B
TA = –40°C to +125°C(6) 100 340 pA B
Input offset current TA = 25°C 1 20 pA A
TA = –40°C to +85°C 5 pA B
TA = –40°C to +125°C 50 pA B
CMRR Common-mode rejection ratio f = DC, TA = 25°C, VCM = 0.75 V to 1.75 V 78 92 dB A
TA = –40°C to +125°C 75 dB B
INPUT
Allowable input differential voltage See Figure 57 ±5 V C
Common-mode input impedance In closed-loop configuration 12 || 2.5 GΩ||pF C
Differential input capacitance In open-loop configuration 0.5 pF C
Most positive input voltage ΔVOS < 5 mV(2) VS+ + 0.2 VS+ + 0.3 V A
TA = –40°C to +125°C VS+ + 0.2 V B
Most negative input voltage ΔVOS < 5 mV(2) VS- – 0.2 VS- – 0.3 V A
TA = –40°C to +125°C VS- – 0.2 V B
Most positive input voltage for main-JFET stage T = 25°C (see Figure 43) VS+ – 2.9 VS+ – 2.5 V C
TA = –40°C to +125°C VS+ – 3 V C
OUTPUT
VOCRH Output voltage range high TA = 25°C, RL = 667 Ω VS+ – 0.12 VS+ – 0.09 V A
TA = –40°C to +125°C, RLOAD = 667 Ω VS+ – 0.15 V B
VOCRL Output voltage range low TA = 25°C, RL = 667 Ω VS– + 0.1 VS–+ 0.06 V A
TA = –40°C to +125°C, RL = 667 Ω VS– + 0.15 V B
IO(max) Linear output drive (sourcing and sinking) TA = 25°C, VO = 1.4 V, RL = 27.5 Ω, VOS < 2 mV, VS+ = 3 V and VS– = –2 V 50 64 mA A
TA = -40°C to 125°C, VO = 0.6 V, VOS < 2 mV, VS+ = 3 V and VS– = –2 V 22 mA B
ISC Output short-circuit current TA = 25°C, TDelay = 5 ms 96 mA B
CL Capacitive load drive < 1 dB peaking, RS = 0 Ω 35 pF C
POWER SUPPLY
VS Operating voltage TA = 25°C 4.75 27 V A
TA = –40°C to +125°C 4.75 27 V B
IQ Quiescent current per channel TA = 25°C 3.05 3.6 4 mA A
TA = –40°C to +125°C 2.8 4.4 mA B
PSRR Power supply rejection ratio  ΔVS = 0.5 V, VCM = 0.5 V(3) 80 100 dB A
TA = –40°C to +125°C 80 dB B
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product VCM = VS+ – 1 V 35 MHz C
Open-loop voltage gain VCM = VS+ – 1 V, f = DC, Vo = 1.5 V to
2.5 V  		80 100 dB A
Input-referred voltage noise VCM = VS+ – 1 V, f = 1 MHz 21 nV/√Hz C
Input offset voltage VCM = VS+ – 1.5 V, no-load 4 mV A
VCM = VS+ – 0.5 V, no-load 4.8 mV A
VCM = VS+ – 0.5 V, TA = –40°C to +125°C, no-load 6.4 mV B
Input bias current VCM = VS+ – 1.5 V 2 20 pA A
VCM = VS+ – 1.5 V, TA = –40°C to +125°C 0.15 0.5 nA B
Common-mode rejection ratio VCM = VS+ – 1.5 V to VS+ – 0.5 V 75 dB B
Power supply rejection ratio VCM = VS+ – 1.5 V, ΔVS = ±0.5 V(3) 75 dB B
CHANNEL MATCHING
Channel-to-channel GBWP mismatch TA = 25°C 3 % C
Channel-to-channel crosstalk f = 100 kHz -93 dBc C
Input offset voltage mismatch TA = 25°C 0.1 2.5 mV A
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) Change in input offset from its value when input is biased to 0 V.
(3) The supply voltages are VS+ = 5 V ± 0.25 V and VS– = 0 V for +PSRR, and VS+ = 5 V and VS– = 0 V ± 0.25 V for –PSRR.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, VS+ = 3.5 V, VS– = –1.5 V, G = 2 V/V, RF = 1 kΩ, CL = 4.7 pF, input and output are biased to 0 V (unless otherwise noted).
(6) Maximum bias current specification is set using ±5σ limits (corresponding to 0.58 DPPM) obtained using the statistical distribution from electrical characterization over temperature of a sample set of 70 units. Maximum specification is not specified by final automated test equipment (ATE) nor by QA sample testing.