SBOS671D September   2018  – December 2022 OPA2828 , OPA828

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Phase-Reversal Protection
      2. 7.3.2  Electrical Overstress
      3. 7.3.3  MUX Friendly Inputs
      4. 7.3.4  Overload Power Limiter
      5. 7.3.5  Noise Performance
        1. 7.3.5.1 Low Noise
      6. 7.3.6  Capacitive Load and Stability
      7. 7.3.7  Settling Time
      8. 7.3.8  Slew Rate
      9. 7.3.9  Full-Power Bandwidth
      10. 7.3.10 Small-Signal Response
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Low Offset Voltage Drift
      13. 7.3.13 Overload Recovery
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 SAR ADC Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Pass Filter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
        2. 8.4.1.2 PowerPAD™ Design Considerations (DGN package only)
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

Figure 8-1 shows the OPA828 configured to enable a wide input voltage range of ±10 V to be attenuated to 0 V to 5 V. The output range of the amplifier is selected based on the full-scale input range of the ADS8860, a 16-bit, 1-MSPS SAR ADC. Supply rails of ±15 V are used so the amplifier can achieve linear swing across the full input range. This design allows the amplifier output to settle to 16-bits within the 290-ns acquisition time of the selected ADC.

The Analog Engineer's Calculator is used to select the resistors and capacitors required to set the signal attenuation as well as the charge bucket between the amplifier and ADC. The input and feedback resistors are chosen to provide a gain of –1/4 (for example, a 4 × attenuation in an inverting configuration). VBIAS is fixed at 2 V to enable the output to swing from 0 V to 5 V. Figure 8-2 shows the simulated settling time of this circuit. To function properly, the output of the amplifier must settle to within ±½ LSB before the end of the ADC acquisition cycle. In this example, using the ADS8860, the output of the amplifier must settle to within ±38.15 µV. Verror is the difference between the expected output and the actual output of the amplifier.

An 820-pF capacitor is added to the feedback to create a low-pass filter with a cutoff frequency of 194 kHz. This filter reduces the noise seen by the ADC and improves the accuracy of the system. The dc transfer function of this circuit is shown in Figure 8-3 and the ac response in shown in Figure 8-4.

For more details and training on configuring an amplifier for an ADC drive, selecting the resistors and capacitor for the charge bucket, and other signal chain topics, visit TI Precision Labs.