SBOS671D September   2018  – December 2022 OPA2828 , OPA828

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Phase-Reversal Protection
      2. 7.3.2  Electrical Overstress
      3. 7.3.3  MUX Friendly Inputs
      4. 7.3.4  Overload Power Limiter
      5. 7.3.5  Noise Performance
        1. 7.3.5.1 Low Noise
      6. 7.3.6  Capacitive Load and Stability
      7. 7.3.7  Settling Time
      8. 7.3.8  Slew Rate
      9. 7.3.9  Full-Power Bandwidth
      10. 7.3.10 Small-Signal Response
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Low Offset Voltage Drift
      13. 7.3.13 Overload Recovery
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 SAR ADC Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Pass Filter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
        2. 8.4.1.2 PowerPAD™ Design Considerations (DGN package only)
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5.1 Low Noise

The OPAx828 are fabricated on a state-of-the-art SiGe precision, high-speed, high-voltage, BiFET wafer process. Patented wafer processing techniques are used to reduce the noise associated with the JFET gate regions. Figure 7-8 shows OPAx828 the noise spectral density.

GUID-37F57C14-3F88-4D31-9B29-116CCFB3883A-low.gif Figure 7-8 Noise Spectral Density vs Frequency