SBOS671D September   2018  – December 2022 OPA2828 , OPA828

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Phase-Reversal Protection
      2. 7.3.2  Electrical Overstress
      3. 7.3.3  MUX Friendly Inputs
      4. 7.3.4  Overload Power Limiter
      5. 7.3.5  Noise Performance
        1. 7.3.5.1 Low Noise
      6. 7.3.6  Capacitive Load and Stability
      7. 7.3.7  Settling Time
      8. 7.3.8  Slew Rate
      9. 7.3.9  Full-Power Bandwidth
      10. 7.3.10 Small-Signal Response
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Low Offset Voltage Drift
      13. 7.3.13 Overload Recovery
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 SAR ADC Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Pass Filter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
        2. 8.4.1.2 PowerPAD™ Design Considerations (DGN package only)
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

MUX Friendly Inputs

Multiplexing is a frequently-used technique to perform data acquisition in multichannel systems with minimal signal-chain requirements. In this context, the role of the multiplexer (MUX) in an acquisition system is to switch between channels and send each signal as fast as possible to a single data converter, maximizing system throughput and minimizing delay. To provide accurate processing, a precision amplifier is placed downstream from the multiplexer to precisely drive the analog-to-digital converter (ADC). Figure 7-4 illustrates this concept.

GUID-2A777936-708A-4980-B753-A717553F07BA-low.gif Figure 7-4 Typical Multiplexed System Block Diagram

In a typical multiplexed application, large transient voltages can often be presented to the input of the op amp driving the ADC. Large input differential voltages are commonly seen during slewing or open-loop operation, which is especially common when switching from one MUX input to another. Traditional precision amplifiers often consist of a differential transistor pair that is protected from large differential transient input voltages with antiparallel diodes between the inputs of the amplifier. These antiparallel diodes are effective at limiting the voltage differential between the inputs to one or two forward diode voltage drops, which protects the precision input devices from damage. However, the antiparallel diodes do have considerable drawbacks such as large inrush currents when turned on. If passive filtering or high source impedance is present, large inrush current can disturb settling time, limiting the throughput of the system and degrading signal-chain precision. The OPAx828 do not need antiparallel diodes to protect the input JFET transistors and are free from large inrush currents, even with differential input voltages as large as ±18 V. These concepts are illustrated in Figure 7-5.

GUID-C548FF79-29EF-410E-B8C4-FFC4F9364BC1-low.gif Figure 7-5 Typical Multiplexed System Block Diagram