Low-power and low-cost video line drivers often buffer digital-to-analog converter (DAC) outputs with a gain of 2 into a doubly-terminated line. Those interfaces typically require a dc blocking capacitor. For a simple design, that interface often has used a very large value blocking capacitor (220μF) to limit tilt, or SAG, across the frames. Figure 8-7 shows one approach to create a very low high-pass pole location using much lower capacitor values. This circuit gives a voltage gain of 2 at the output pin with a high-pass pole at 8Hz. Given the 150Ω load, a simple blocking capacitor approach requires a 133μF value. The two much-lower-valued capacitors give this same low-pass pole using this simple SAG correction circuit of Figure 8-7.

The input is shifted slightly positive in Figure 8-7 using the voltage divider from the positive supply. This shift gives about a 200mV input dc offset that shows up at the output pin as a 400mV dc offset when the DAC output is at zero current during the sync tip portion of the video signal. This offset acts to hold the output in the linear operating region. This configuration passes on any power-supply noise to the output with a gain of approximately –20dB; therefore, good supply decoupling is recommended on the power-supply pin. Figure 8-6 shows the frequency response for the circuit of Figure 8-7. This plot shows the 8Hz low-frequency high-pass pole and a high-end cutoff at approximately 100MHz.

Figure 8-6 Video-Line-Driver Response to Matched Load

Figure 8-7 Video Line Driver With SAG Correction