SBOSAB2A february   2023  – july 2023 OPA2863-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = ±5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: VS = 3 V to 10 V
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
        1. 8.3.2.1 Overload Power Limit
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Side Current Sensing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Front-End Gain and Filtering
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2.1 Overload Power Limit

The OPA2863-Q1 includes overload power limiting that limits the increase in device quiescent current with output saturated to either of the supplies. Typically, when an amplifier output saturates, the two inputs are pulled apart, which can enable the slew-boost circuit. The input differential voltage is an error voltage in negative feedback that the amplifier core nullifies by engaging the slew-boost circuit and driving the output stage deeper into saturation. After the input to an amplifier attains a value large enough to saturate the output, any further increase in this input excitation results in a finite input differential voltage. As the output stage transistor is pushed deeper into saturation, the base-to-collector current gain (hFE) drops with an increase in the base and collector current, and an increase in the device quiescent current. This increase in quiescent current can cause a catastrophic failure in multichannel, high-gain, high-density front-end designs, and reduce operating lifetime in portable, battery-powered systems.

The OPA2863-Q1 overload power limiting includes an intelligent output saturation-detection circuit that limits the device quiescent current to 2.2-mA per channel under dc overload conditions. This increase in quiescent current is smaller with ac input or output and output saturation duration for only a fraction of the overall signal time period. Table 8-1 compares the increase in quiescent current with 50‑mV input overdrive for OPA2863-Q1 and other voltage-feedback amplifiers without overload power limit.

Table 8-1 Quiescent Current with Saturated Outputs
DEVICEINPUT DIFFERENTIAL VOLTAGEQUIESCENT CURRENT DURING OVERLOADINCREASE IN IQ FROM STEADY-STATE CONDITION
OPA2863-Q1 with overload power limit50 mV1.1 mA1.57 ×
Competitor amplifier without overload power limit50 mV1.96 mA3.43 ×