SBOS982J june   2020  – june 2023 OPA2863 , OPA4863 , OPA863

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: OPA863
    5. 7.5  Thermal Information: OPA2863
    6. 7.6  Thermal Information: OPA4863
    7. 7.7  Electrical Characteristics: VS = 10 V
    8. 7.8  Electrical Characteristics: VS = 3 V
    9. 7.9  Typical Characteristics: VS = 10 V
    10. 7.10 Typical Characteristics: VS = 3 V
    11. 7.11 Typical Characteristics: VS = 3 V to 10 V
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
        1. 8.3.2.1 Overload Power Limit
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Side Current Sensing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Front-End Gain and Filtering
      3. 9.2.3 Low-Power SAR ADC Driver and Reference Buffer
      4. 9.2.4 Variable Reference Generator Using MDAC
      5. 9.2.5 Clamp-On Ultrasonic Flow Meter
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Considerations
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Electrical Characteristics: VS = 10 V

at VS+ = 5 V, VS– = –5 V, G = 1 V/V, RF = 0 Ω for G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to mid-supply, input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1, < 1 dB peaking 110 MHz
GBWP Gain-bandwidth product 50 MHz
LSBW Large-signal bandwidth VOUT = 2 VPP 17 MHz
Bandwidth for 0.1-dB flatness VOUT = 20 mVPP 15 MHz
SR Slew rate VOUT = 2–V step, G = –1 105 V/µs
Rise, fall time VOUT = 200–mV step 9 ns
Settling time to 0.1% VOUT = 2–V step 57 ns
Settling time to 0.01% 70
Overshoot/undershoot VOUT = 2–V step 1 %
Overdrive recovery time G = –1, 0.5 V overdrive beyond supplies 70 ns
G = 1, 0.5 V overdrive beyond supplies 100
HD2 Second-order harmonic distortion f = 20 kHz, VOUT = 2 VPP –129 dBc
HD3 Third-order harmonic distortion –138
HD2 Second-order harmonic distortion f = 100 kHz, VOUT = 2 VPP –107 dBc
HD3 Third-order harmonic distortion –125
eN Input voltage noise Flatband, 1/f corner at 25 Hz 5.9 nV/√Hz
iN Input current noise Flatband, 1/f corner at 2 kHz 0.4 pA/√Hz
Closed-loop output impedance f = 1 MHz 0.2 Ω
Channel-to-channel crosstalk f = 1 MHz, VOUT = 2 VPP, OPA2863 –124 dBc
DC PERFORMANCE
AOL Open-loop voltage gain VOUT = ±2.5 V 110 128 dB
VOS Input-referred offset voltage –1.3 ±0.4 1.3 mV
Input offset voltage drift TA = –40°C to +125°C,
D, DBV-5, RUN and DGK packages		 –3.5 ±1 3.5 µV/°C
TA = –40°C to +125°C, PW package –4 ±1 4
TA = 0°C to +85°C, DBV-6 package –4.4 ±1 4.4
TA = –40°C to +125°C, DBV-6 package –4.9 ±1 4.9
Input bias current TA ≅ 25°C 0.3 0.73 µA
TA = –40°C to +85°C 1.2
TA = –40°C to +125°C 1.6
Input bias current drift TA = –40°C to +125°C ±3 7.6 nA/°C
Input offset current –30 ±10 30 nA
INPUT
Input common-mode voltage range VS––0.2 VS++0.2 V
CMRR Common-mode rejection ratio VCM = VS– – 0.2 V to VS+ – 1.6 V 100 120 dB
Input impedance common-mode 650 || 0.8 MΩ || pF
Input impedance differential mode 200 || 0.5 kΩ || pF
OUTPUT
VOL Output voltage, low TA ≅ 25°C VS–+0.14 VS–+0.2 V
TA = –40°C to +125°C VS–+0.15 VS–+0.22
VOH Output voltage, high TA ≅ 25°C VS+–0.2 VS+–0.14 V
TA = –40°C to +125°C VS+–0.2 VS+–0.15
Linear output drive (sourcing/sinking) VOUT = ±2.5 V, ΔVOS < 1 mV 
OPA863 and OPA2863(1)		 25 30 mA
Short-circuit current 45 mA
POWER SUPPLY
IQ Quiescent current per amplifier TA ≅ 25°C 700 970 µA
TA = –40°C to +125°C 1280
PSRR Power-supply rejection ratio ΔVS = ±2 V(2) 100 120 dB
POWER DOWN (Pin Must be Driven)
Enable voltage threshold  Specified on above VS+ – 0.5 V 4.5 V
Disable voltage threshold Specified off below VS+ – 1.5 V 3.5 V
Power-down quiescent current per channel PD ≤ VS+ – 1.5 V 2 3.3 µA
Power-down pin bias current 2 50 nA
Turn-on time delay 6 µs
Turn-off time delay 4.5 µs
AUXILIARY INPUT STAGE
Gain-bandwidth product 50 MHz
Input voltage noise Flatband, 1/f corner at 25 Hz 6 nV/√Hz
Input current noise Flatband, 1/f corner at 100 Hz 0.4 pA/√Hz
Input-referred offset voltage –1.3 ±0.15 1.3 mV
Input bias current TA ≅ 25°C 0.2 0.6 µA
TA = –40°C to +125°C 0.2 1.3
Common-mode rejection ratio VCM = 4.1 V to 5.2 V 100 120 dB
Power supply rejection ratio ΔVS = ±0.6 V 100 120 dB
(1) Change in input offset voltage from no-load condition.
(2)
Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.