SBOSAG6 November   2023 OPA2994-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Unlimited Capacitive Load Drive
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Common-Mode Voltage Range
      4. 6.3.4 Phase Reversal Protection
      5. 6.3.5 Electrical Overstress
      6. 6.3.6 Overload Recovery
      7. 6.3.7 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 24 V (±1.35 V to ±12 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OFFSET VOLTAGE
VOSInput offset voltageVCM = V–±0.2±1mV
TA = –40°C to 125°C±1.2
dVOS/dTInput offset voltage driftVCM = V–TA = –40°C to 125°C±0.17µV/℃
PSRRInput offset voltage versus power supplyVCM = V–, VS = 5 V to 24 VTA = –40°C to 125°C±3.5±22μV/V
PSRRInput offset voltage versus power supplyVCM = V–, VS = 2.7 V to 24 VTA = –40°C to 125°C±60(1)μV/V
DC channel separation1µV/V
INPUT BIAS CURRENT
IBInput bias current±400±1500nA
IOSInput offset current±2nA
NOISE
ENInput voltage noisef = 0.1 Hz to 10 Hz 1.8μVPP
 0.3 µVRMS
eNInput voltage noise densityf = 1 kHz12 nV/√Hz
f = 10 kHz 11 
iNInput current noise densityf = 1 kHz 1 pA/√Hz
INPUT VOLTAGE RANGE
VCMCommon-mode input voltage range(V–) – 0.1(V+) + 0.1V
VDiffDifferential input voltage range±0.5V
CMRRCommon-mode rejection ratioVS = 24 V, V– < VCM < (V+) – 2 V (Main Input Pair)TA = –40°C to 125°C115135dB
VS = 5 V, V– < VCM < (V+) – 2 V (Main Input Pair)(1)105120
VS = 2.7 V, V– < VCM < (V+) – 2 V (Main Input Pair)100
VS = 2.7 – 24 V, (V+) – 1 V < VCM < V+ (Aux Input Pair)95
(V+) – 2 V < VCM < (V+) – 1 VTA = –40°C to 125°CSee 
INPUT IMPEDANCE
ZIDDifferential10 || 3MΩ || pF
ZICMCommon-mode1 || 1TΩ || pF
OPEN-LOOP GAIN
AOLOpen-loop voltage gainVS = 24 V, VCM = VS / 2,
(V–) + 1 V < VO < (V+) –  1 V		8087dB
TA = –40°C to 125°C87
VS = 5 V, VCM = VS / 2,
(V–) + 1 V < VO < (V+) –  1 V(1)		7580
TA = –40°C to 125°C80
VS = 2.7 V, VCM = VS / 2,
(V–) + 1 V < VO < (V+) –  1 V(1)		7580
TA = –40°C to 125°C80
FREQUENCY RESPONSE
GBWGain-bandwidth product25MHz
SRSlew rateVS = 24 V, VSTEP = 10 V, G = +1, CL = 20 pF(6)18V/μs
tSSettling timeTo 0.1%, VS = 24 V, VSTEP = 10 V, G = +1, CL = 50 pF0.15µs
To 0.1%, VS = 24 V, VSTEP = 10 V, G = +1, CL = 500 pF0.5
To 0.01%, VS = 24 V, VSTEP = 10 V, G = +1, CL = 50 pF0.65
To 0.01%, VS = 24 V, VSTEP = 10 V, G = +1, CL = 500 pF1
Phase marginG = +1, RL = 10 kΩ, CL = 20 pF55°
Overload recovery timeVIN  × gain > VS200ns
THD+NTotal harmonic distortion + noiseVS = 24 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ0.0001%
120dB
VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω0.001%
100dB
VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω0.00032%
110dB
OUTPUT
 Voltage output swing from railPositive and negative
rail headroom		VS = 24 V, RL = no load 35mV
VS = 24 V, RL = 10 kΩ 4555
VS = 24 V, RL = 2 kΩ 6070
VS = 5 V, RL = no load35
VS = 5 V, RL = 10 kΩ4045
VS = 5 V, RL = 2 kΩ4550
VS = 2.7 V, RL = no load 30
VS = 2.7 V, RL = 10 kΩ 3540
VS = 2.7 V, RL = 2 kΩ 4050
ISCShort-circuit currentVS = 24 V±62±150mA
VS = 5 V(1)±50±100
VS = 2.7 V(1)±45±65
CLOADCapacitive load driveUnlimited; See pF
ZOOpen-loop output impedanceIO = 0 ASee Ω
POWER SUPPLY
IQQuiescent current per amplifierIO = 0 A1.251.7mA
IQQuiescent current per amplifierTA = –40°C to 125°C2.1mA
(1) Specified by characterization only.
(2) See for more information.