SBOSAI0B December   2023  – September 2024 OPA310-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Voltage
      2. 6.3.2 Rail-to-Rail Input
      3. 6.3.3 Rail-to-Rail Output
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 Overload Recovery
      6. 6.3.6 EMI Rejection
      7. 6.3.7 ESD and Electrical Overstress
      8. 6.3.8 Input ESD Protection
      9. 6.3.9 Shutdown Function
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 OPAx310-Q1 Low-Side, Current Sensing Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4.     Trademarks
    5. 8.4 Electrostatic Discharge Caution
    6. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
  • DBV|6
  • DCK|5
  • DCK|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.9 Shutdown Function

The OPAx310-Q1 S devices feature SHDN pins that disable the op amp, placing the op amp into a low-power standby mode. In this mode, the op amp typically consumes less than 500nA at room temperature. The SHDN pins are active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown feature lies around 500mV (typical) and does not change with respect to the supply voltage. Hysteresis has been included in the switching threshold to provide for smooth switching characteristics. To make sure of optimal shutdown behavior, the SHDN pins must be driven with valid logic signals. A valid logic low is defined as a voltage between V– and (V–) + 0.2V. A valid logic high is defined as a voltage between (V–) + 1.2V and V+. To enable the amplifier, the SHDN pins must be driven to a valid logic high. To disable the amplifier, the SHDN pins must be driven to a valid logic low. TI highly recommends that the shutdown pin be connected to a valid high or a low voltage or driven. The maximum voltage allowed at the SHDN pins is (V+) + 0.5V. Exceeding this voltage level damages the device.

The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature can be used to greatly reduce the average current and extend battery life. The enable and disable time is targeted to be under 1µs for full shutdown of all channels. When disabled, the output assumes a high-impedance state. This architecture allows the OPAx310S-Q1 to be operated as a gated amplifier (or to have the device output multiplexed onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load resistance increases. To make sure that shutdown (disable) is within a specific shutdown time, the specified 10-kΩ load to midsupply (VS / 2) is required.