SBOSA13A May   2022  – August 2022 OPA3S2859

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Programmable Gain
      2. 8.3.2 Slew Rate
      3. 8.3.3 Input and ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply and Single-Supply Operation
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Gain Select Mode (SEL)
      4. 8.4.4 Latch Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.2 Layout Examples

Figure 11-1 shows a typical layout around the OPA3S2859 based on the evaluation module. The smallest decoupling capacitors were placed as close as possible to the DUT with wide metal area to minimize inductance. Special attention was placed on the feedback network layout to optimize the design for a typical application using 1 kΩ, 10 kΩ, and 100 kΩ feedback resistors. Figure 11-2 shows more details. The black colored areas under the input and feedback traces show the voids cut in the ground plane underneath the traces to minimize capacitance to ground as much as possible.

Figure 11-1 General Layout Example

Figure 11-2 shows an example of a feedback network from the evaluation module optimized to reduce the capacitive coupling between the feedback and output traces. Ground plane is poured between each of the feedback traces and component footprints as much as possible for the best isolation. A small isoation resistor (RISO) is connected between the output and feedback trace to help isolate the trace capacitance from being directly connected to the DUT output. Additionally, the ground plane is removed from under the feedback trace to further reduce the parasitic capacitance to ground created by the additional trace length required for the feedback network.

Figure 11-2 Feedback Network Layout Recommendations