SBOS641D June   2012  – September 2016 OPA4188

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Zero-Drift Amplifier Portfolio
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: High-Voltage Operation, VS = ±4 V to ±18 V (VS = 8 V to 36 V)
    6. 7.6 Electrical Characteristics: Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V)
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Phase-Reversal Protection
      2. 8.3.2 Capacitive Load and Stability
      3. 8.3.3 Electrical Overstress
      4. 8.3.4 EMI Rejection
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Operating Characteristics
    2. 9.2 Typical Applications
      1. 9.2.1 Second Order Low Pass Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Discrete INA + Attenuation for ADC With a 3.3-V Supply
      3. 9.2.3 RTD Amplifier With Linearization
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Device Support
        1. 12.1.1.1 Development Support
          1. 12.1.1.1.1 TINA-TI (Free Software Download)
          2. 12.1.1.1.2 TI Precision Designs
          3. 12.1.1.1.3 WEBENCH® Filter Designer
      2. 12.1.2 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
OPA4188 tc_histo_voff_bos525.gif
Figure 1. Offset Voltage Production Distribution
OPA4188 tc_vo-tmp_bos641.gif
Figure 3. Offset Voltage vs Temperature
OPA4188 tc_vos-vcm_18v_bos525.gif
Figure 5. Offset Voltage vs Common-Mode Voltage
OPA4188 tc_ib_ios-vcm_bos525.gif
Figure 7. IB and IOS vs Common-Mode Voltage
OPA4188 tc_vo_swing-io_bos525.gif
Figure 9. Output Voltage Swing vs Output Current (Maximum Supply)
OPA4188 tc_cmrr-tmp_2v_bos641.gif
Figure 11. CMRR vs Temperature
OPA4188 tc_psrr-tmp_bos641.gif
Figure 13. PSRR vs Temperature
OPA4188 tc_noise_spec-frq_bos525.gif
Figure 15. Input Voltage Noise Spectral Density vs Frequency
OPA4188 tc_thdn-outamp_bos525.gif
Figure 17. THD+N vs Output Amplitude
OPA4188 tc_iq-tmp_bos641.gif
Figure 19. Quiescent Current vs Temperature
OPA4188 tc_cloop_g-frq_bos525.gif
Figure 21. Closed-Loop Gain vs Frequency
OPA4188 tc_oloop_iout-frq_bos525.gif
Figure 23. Open-Loop Output Impedance vs Frequency
OPA4188 tc_sm_oshoot-cl_neg_bos525.gif
Figure 25. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
OPA4188 tc_oload_pos_bos525.gif
Figure 27. Positive Overload Recovery
OPA4188 tc_sm_step_pos_bos525.gif
Figure 29. Small-Signal Step Response (100 mV)
OPA4188 tc_lg_step_pos_bos525.gif
Figure 31. Large-Signal Step Response
OPA4188 tc_lg_t_pos_bos525.gif
Figure 33. Large-Signal Settling Time (10-V Positive Step)
OPA4188 tc_isc-tmp_bos641.gif
Figure 35. Short Circuit Current vs Temperature
OPA4188 tc_ch_sep-frq_bos525.gif
Figure 37. Channel Separation vs Frequency
OPA4188 tc_histo_voff_drift_bos525.gif
Figure 2. Offset Voltage Drift Distribution
OPA4188 tc_vos-vcm_2v_bos525.gif
Figure 4. Offset Voltage vs Common-Mode Voltage
OPA4188 tc_vos-vsupply_bos525.gif
Figure 6. Offset Voltage vs Power Supply
OPA4188 tc_ibias-tmp_bos641.gif
Figure 8. Input Bias Current vs Temperature
OPA4188 tc_cmrr_psrr-frq_bos525.gif
Figure 10. CMRR and PSRR vs Frequency
(Referred-to-Input)
OPA4188 tc_cmrr-tmp_18v_bos641.gif
Figure 12. CMRR vs Temperature
OPA4188 tc_noise_bos525.gif
Figure 14. 0.1-Hz to 10-Hz Noise
OPA4188 tc_thdn-frq_bos525.gif
Figure 16. THD+N Ratio vs Frequency
OPA4188 tc_iq-vs_bos525.gif
Figure 18. Quiescent Current vs Supply Voltage
OPA4188 tc_g_ph-frq_bos525.png
Figure 20. Open-Loop Gain and Phase vs Frequency
OPA4188 tc_oloop_g-tmp_bos641.gif
Figure 22. Open-Loop Gain vs Temperature
OPA4188 tc_sm_oshoot-cl_pos_bos525.gif
Figure 24. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
OPA4188 tc_no_phase_bos525.gif
Figure 26. No Phase Reversal
OPA4188 tc_oload_neg_bos525.gif
Figure 28. Negative Overload Recovery
OPA4188 tc_sm_step_neg_bos525.gif
Figure 30. Small-Signal Step Response (100 mV)
OPA4188 tc_lg_step_neg_bos525.gif
Figure 32. Large-Signal Step Response
OPA4188 tc_lg_t_neg_bos525.gif
Figure 34. Large-Signal Settling Time (10-V Negative Step)
OPA4188 tc_max_vo-frq_bos525.gif
Figure 36. Maximum Output Voltage vs Frequency
OPA4188 tc_emirr-frq_bos525.gif
Figure 38. EMIRR IN+ vs Frequency