SBOS701D December   2015  – August 2021 OPA191 , OPA2191 , OPA4191

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA191
    5. 6.5 Thermal Information: OPA2191
    6. 6.6 Thermal Information: OPA4191
    7. 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
    8. 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Input Offset Voltage Drift
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Protection Circuitry
      2. 8.3.2 EMI Rejection
      3. 8.3.3 Phase Reversal Protection
      4. 8.3.4 Thermal Protection
      5. 8.3.5 Capacitive Load and Stability
      6. 8.3.6 Common-Mode Voltage Range
      7. 8.3.7 Electrical Overstress
      8. 8.3.8 Overload Recovery
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Low-side Current Measurement
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 16-Bit Precision Multiplexed Data-Acquisition System
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Slew Rate Limit for Input Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI™ SImulation Software (Free Download)
        2. 12.1.1.2 TI Precision Designs
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Typical Characteristics

at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

Table 6-1 Table of Graphs
DESCRIPTIONFIGURE
Offset Voltage Production DistributionFigure 6-1, Figure 6-2, Figure 6-3, Figure 6-4, Figure 6-5, Figure 6-6
Offset Voltage Drift DistributionFigure 6-7, Figure 6-8,
Offset Voltage vs TemperatureFigure 6-9, Figure 6-10
Offset Voltage vs Common-Mode VoltageFigure 6-11, Figure 6-12
Offset Voltage vs Power SupplyFigure 6-13
Open-Loop Gain and Phase vs FrequencyFigure 6-14
Closed-Loop Gain and Phase vs FrequencyFigure 6-15
Input Bias Current vs Common-Mode VoltageFigure 6-16
Input Bias Current vs TemperatureFigure 6-17
Output Voltage Swing vs Output Current (maximum supply)Figure 6-18, Figure 6-19
CMRR and PSRR vs FrequencyFigure 6-20
CMRR vs TemperatureFigure 6-21
PSRR vs TemperatureFigure 6-22
0.1-Hz to 10-Hz NoiseFigure 6-23
Input Voltage Noise Spectral Density vs FrequencyFigure 6-24
THD+N Ratio vs FrequencyFigure 6-25
THD+N vs Output AmplitudeFigure 6-26
Quiescent Current vs Supply VoltageFigure 6-27
Quiescent Current vs TemperatureFigure 6-28
Open Loop Gain vs TemperatureFigure 6-29, Figure 6-30
Open Loop Output Impedance vs FrequencyFigure 6-31
Small Signal Overshoot vs Capacitive Load (100-mV output step)Figure 6-32, Figure 6-33
No Phase ReversalFigure 6-34
Overload RecoveryFigure 6-35
Small-Signal Step Response (100 mV)Figure 6-36, Figure 6-37
Large-Signal Step ResponseFigure 6-38, Figure 6-39
Settling TimeFigure 6-40, Figure 6-41, Figure 6-42, Figure 6-43
Short-Circuit Current vs TemperatureFigure 6-44
Maximum Output Voltage vs FrequencyFigure 6-45
Propagation Delay Rising EdgeFigure 6-46
Propagation Delay Falling EdgeFigure 6-47
GUID-3814E06C-E848-4672-AA0E-D4FEFF4C9696-low.gif
TA = 25°C
Figure 6-1 Offset Voltage Production Distribution
GUID-FD733306-5E95-42F5-90EF-4A15BA25BA97-low.gif
TA = 85°C
Figure 6-3 Offset Voltage Production Distribution
GUID-C7073127-09A0-4FF5-9FBB-5019A583D840-low.gif
TA = –25°C
Figure 6-5 Offset Voltage Production Distribution
GUID-93D6C154-170C-40DA-A6F3-7E926C1E06B0-low.png
TA = –40°C to +125°C, SOIC package
Figure 6-7 Offset Voltage Drift Distribution
GUID-9E2642B1-C7BD-44DF-AC1F-08804D62F412-low.gif
Statistical distribution
Figure 6-9 Offset Voltage vs Temperature
GUID-712CC37F-42C1-40C7-944D-3833B4C3B74C-low.pngFigure 6-11 Offset Voltage vs Common-Mode Voltage
GUID-04F77ACD-53DA-4463-8E3E-DC374BB80F25-low.gif
30 typical units
Figure 6-13 Offset Voltage vs Power Supply
GUID-7B121E9A-90CD-495A-AE88-A7E006E197DA-low.pngFigure 6-15 Closed-Loop Gain vs Frequency
GUID-4E6325BF-2B65-4E77-8F03-740285375244-low.png
 
Figure 6-17 Input Bias Current vs Temperature
GUID-0F4A98EB-ED47-4264-A24B-C84746338683-low.gif
Sinking
Figure 6-19 Output Voltage Swing
vs Output Current
GUID-ECAC9B92-4543-4332-9BF4-FCECF5C6C946-low.png
 
Figure 6-21 CMRR vs Temperature
GUID-489DAC6D-8AEF-4EAE-B85F-D99A7584B3D4-low.gif
 
Figure 6-23 0.1-Hz to 10-Hz Noise
GUID-4E4CF76B-F908-4100-BE45-4791E23D8288-low.png
 
Figure 6-25 THD+N vs Frequency
GUID-3BE2EC6E-2899-4755-B0A1-B9B1D5CB4E9A-low.gif
 
Figure 6-27 Quiescent Current vs Supply Voltage
GUID-B40EF863-C4CC-4E91-A55F-770A1474003D-low.png
RL = 10 kΩ
Figure 6-29 Open-Loop Gain vs Temperature
GUID-5B166855-B637-4A0D-A01F-C2D1848D71F3-low.gif
 
Figure 6-31 Open-Loop Output Impedance
vs Frequency
GUID-FB7C3C8B-1E01-4A50-B4A0-89A260A5034A-low.png
G = –1, 100-mV output step
Figure 6-33 Small-Signal Overshoot
vs Capacitive Load
GUID-F3AFEF95-5E28-45C1-964B-1EB21C66DB92-low.gif
VS = ±18 V, G = –10 V/V
Figure 6-35 Overload Recovery
GUID-E20A6D62-7649-4848-BCB9-A89F2296D781-low.png
G = –1, RL = 1 kΩ, CL = 10 pF
Figure 6-37 Small-Signal Step Response
GUID-1BA9D419-5182-4864-BB13-846492DFD3C4-low.png
G = –1, RL = 1 kΩ, CL = 10 pF
Figure 6-39 Large-Signal Step Response
GUID-3144F842-1E1D-4E36-8273-C9D8A0C61066-low.gif
Gain = 1, 2-V step, falling, step applied at t = 0 µs
Figure 6-41 0.01% Settling Time
GUID-C6E524E9-A39A-4341-A2B6-DFD664C83F29-low.gif
Gain = 1, 5-V step, falling, step applied at t = 0 µs
Figure 6-43 0.01% Settling Time
GUID-4C7F8DE3-EBA0-46A1-9DCE-026B9B92D842-low.png
 
Figure 6-45 Maximum Output Voltage vs Frequency
GUID-86E0C694-2C7B-4CCA-BDB1-2554D3ED240B-low.png
 
Figure 6-47 Propagation Delay Falling Edge
GUID-554EF107-A6DD-4E54-8E26-7456DFF72D97-low.gif
TA = 125°C
Figure 6-2 Offset Voltage Production Distribution
GUID-EAA6482F-0E73-4ABB-A39F-F53CB5F68912-low.gif
TA = 0°C
Figure 6-4 Offset Voltage Production Distribution
GUID-FB95A4FC-F8BA-44D4-BCF0-2E72E859A102-low.gif
TA = –40°C
Figure 6-6 Offset Voltage Production Distribution
GUID-F151D54C-DAC9-4E15-BE2D-88F9657F7E8E-low.png
TA = 0°C to 85°C, SOIC package
Figure 6-8 Offset Voltage Drift Distribution
GUID-838FEE27-9B84-4B6F-A173-BCF541D144F1-low.png
4 typical units
Figure 6-10 Offset Voltage vs Temperature
GUID-BF9A203C-7B79-4198-8AB3-1316765838C3-low.pngFigure 6-12 Offset Voltage vs Common-Mode Voltage in Transition Region
GUID-4C3EC33F-C2E1-4CE9-A1E8-3C10B8CFF125-low.png
 
Figure 6-14 Open-Loop Gain and Phase
vs Frequency
GUID-FBB7F333-B049-479E-8962-0CCCE48987A2-low.pngFigure 6-16 Input Bias Current
vs Common-Mode Voltage
GUID-B1547622-39F3-4067-BAC4-F8033D72243A-low.gif
Sourcing
Figure 6-18 Output Voltage Swing
vs Output Current
GUID-2FFB972B-BF7E-4043-8407-C0DCFDD54416-low.png
 
Figure 6-20 CMRR and PSRR vs Frequency
GUID-231C3975-C5A1-4A01-98AE-A302152EE7FD-low.png
 
Figure 6-22 PSRR vs Temperature
GUID-1C4DD1ED-E651-47C1-A5FD-1A610CD21834-low.png
 
Figure 6-24 Input Voltage Noise Spectral Density vs Frequency
GUID-A7439334-CDD4-4D3C-B35D-89E0C90F4228-low.gif
 
Figure 6-26 THD+N vs Output Amplitude
GUID-73F798E9-9BF0-47D6-AE42-EB6603BBAA20-low.png
 
Figure 6-28 Quiescent Current vs Temperature
GUID-0996783F-B763-41DD-B487-0DE6AD03E9EF-low.png
RL = 2 kΩ
Figure 6-30 Open-Loop Gain vs Temperature
GUID-B220888A-B532-4CAB-9E34-3D1B52B0E470-low.png
G = 1, 100-mV output step
Figure 6-32 Small-Signal Overshoot
vs Capacitive Load (100-mV Output Step)
GUID-FD051949-CBD3-4E25-B4DA-B8958CC08A5C-low.gif
 
Figure 6-34 No Phase Reversal
GUID-E348A458-077A-4B77-A2B5-DBD477C23673-low.png
G = 1, CL = 10 pF
Figure 6-36 Small-Signal Step Response
GUID-0E07DCF9-4FD3-45D4-92AD-730F313AF074-low.png
G = 1, CL = 10 pF
Figure 6-38 Large-Signal Step Response
GUID-94BE86AE-C08D-4C7A-B0E4-E254504F6F58-low.gif
Gain = 1, 2-V step, rising, step applied at t = 0 µs
Figure 6-40 0.01% Settling Time
GUID-F56A61FF-081F-4AF6-8155-8C4F7CA4AF91-low.gif
Gain = 1, 5-V step, rising, step applied at t = 0 µs
Figure 6-42 0.01% Settling Time
GUID-D4E24887-04E8-44FE-A621-EA6346BD031C-low.png
 
Figure 6-44 Short-Circuit Current vs Temperature
GUID-7CF3532B-5BD2-46D0-AF62-1A892C5E3FF5-low.png
 
Figure 6-46 Propagation Delay Rising Edge