SBOS079C March   1999  – February 2023 OPA2277 , OPA277 , OPA4277

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA277
    5. 6.5 Thermal Information: OPA2277
    6. 6.6 Thermal Information: OPA4277
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Offset Voltage Adjustment
      3. 7.3.3 Input Protection
      4. 7.3.4 Input Bias Current Cancellation
      5. 7.3.5 EMI Rejection Ratio (EMIRR)
        1. 7.3.5.1 EMIRR IN+ Test Configuration
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Second-Order, Low-Pass Filter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Load Cell Amplifier
      3. 8.2.3 Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction Compensation
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 DRM Package (8-Pin VSON)
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 9.1.1.3 DIP-Adapter-EVM
        4. 9.1.1.4 DIYAMP-EVM
        5. 9.1.1.5 TI Reference Designs
        6. 9.1.1.6 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • N|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-639F9EED-469F-4ADF-BDA8-C02D5E736F11-low.gifFigure 5-1 OPA277 P Package, 8-Pin PDIP and D Package, 8-Pin SOIC (Top View)
GUID-C529A7B3-4E3A-4736-9327-CF5CA46D50DC-low.gifFigure 5-2 OPA277 DRM Package, 8-Pin VSON (Top View)
Table 5-1 Pin Functions: OPA277
PIN TYPE DESCRIPTION
NAME NO.
–In 2 Input Inverting input
+In 3 Input Noninverting input
NC 5 — No internal connection (can be left floating)
Offset Trim 1 — Input offset voltage trim (leave floating if not used)
Offset Trim 8 — Input offset voltage trim (leave floating if not used)
Output 6 Output Output
V– 4 — Negative (lowest) power supply
V+ 7 — Positive (highest) power supply
GUID-2BD9199C-C666-408E-9D69-7CD19CF281F6-low.gifFigure 5-3 OPA2277 P Package, 8-Pin PDIP and D Package, 8-Pin SOIC (Top View)
GUID-6E22B216-DB88-496F-9197-7F48EBB8B816-low.gifFigure 5-4 OPA2277 DRM Package, 8-Pin VSON (Top View)
Table 5-2 Pin Functions: OPA2277
PIN TYPE DESCRIPTION
NAME D (SOIC), P (PDIP) DRM (VSON)
–In A 2 2 Input Inverting input channel A
–In B 6 6 Input Inverting input channel B
+In A 3 3 Input Noninverting input channel A
+In B 5 5 Input Noninverting input channel B
Out A 1 1 Output Output channel A
Out B 7 8 Output Output channel B
V– 4 4 — Negative (lowest) power supply
V+ 8 7 — Positive (highest) power supply
GUID-8F485645-AB5A-4760-8C32-99C1F602ACAF-low.gif Figure 5-5 OPA4277 P Package, 14-Pin PDIP and D Package, 14-Pin SOIC (Top View)
Table 5-3 Pin Functions: OPA4277
PIN TYPE DESCRIPTION
NAME NO.
–In A 2 Input Inverting input channel A
–In B 6 Input Inverting input channel B
–In C 9 Input Inverting input channel C
–In D 13 Input Inverting input channel D
+In A 3 Input Noninverting input channel A
+In B 5 Input Noninverting input channel B
+In C 10 Input Noninverting input channel C
+In D 12 Input Noninverting input channel D
Out A 1 Output Output channel A
Out B 7 Output Output channel B
Out C 8 Output Output channel C
Out D 14 Output Output channel D
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply