SBOS703F April   2014  – October 2016 OPA2316 , OPA316 , OPA4316

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA316
    5. 6.5 Thermal Information: OPA2316
    6. 6.6 Thermal Information: OPA2316S
    7. 6.7 Thermal Information: OPA4316
    8. 6.8 Electrical Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Input and ESD Protection
      4. 7.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 7.3.5 EMI Susceptibility and Input Filtering
      6. 7.3.6 Rail-to-Rail Output
      7. 7.3.7 Capacitive Load and Stability
      8. 7.3.8 Overload Recovery
      9. 7.3.9 DFN Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Configurations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Amplifier Selection
        2. 8.2.2.2 Passive Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
      1. 10.6 Electrostatic Discharge Caution
      2. 10.7 Glossary
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage 7 V
Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V
Differential (V+) – (V–) + 0.2 V
Current(2) –10 10 mA
Output short-circuit(3) Continuous
TA Operating temperature –55 150 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted).
VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).
MIN MAX UNIT
VS Supply voltage 1.8 5.5 V
Specified temperature –40 125 °C

6.4 Thermal Information: OPA316

THERMAL METRIC(1) OPA316 UNIT
DBV (SOT23) DCK (SC70)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance(2) 221.7 263.3 °C/W
RθJC(top) Junction-to-case(top) thermal resistance(3) 144.7 75.5 °C/W
RθJB Junction-to-board thermal resistance(4) 49.7 51 °C/W
ψJT Junction-to-top characterization parameter(5) 26.1 1 °C/W
ψJB Junction-to-board characterization parameter(6) 49 50.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.5 Thermal Information: OPA2316

THERMAL METRIC(1) OPA2316 UNIT
D (SO) DGK (MSOP) DRG (DFN)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance(2) 127.2 186.6 56.3 °C/W
RθJC(top) Junction-to-case(top) thermal resistance(3) 71.6 78.8 72.2 °C/W
RθJB Junction-to-board thermal resistance(4) 68.2 107.9 31 °C/W
ψJT Junction-to-top characterization parameter(5) 22 15.5 2.3 °C/W
ψJB Junction-to-board characterization parameter(6) 67.6 106.3 21.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A 10.9 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.6 Thermal Information: OPA2316S

THERMAL METRIC(1) OPA2316S UNIT
DGS (MSOP) QFN (RUG)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance(2) 189.6 158 °C/W
RθJC(top) Junction-to-case(top) thermal resistance(3) 73.9 52 °C/W
RθJB Junction-to-board thermal resistance(4) 110.7 88 °C/W
ψJT Junction-to-top characterization parameter(5) 13.4 1 °C/W
ψJB Junction-to-board characterization parameter(6) 109.1 87 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.7 Thermal Information: OPA4316

THERMAL METRIC(1) OPA4316 UNIT
PW (TSSOP) D (SOIC)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance(2) 117.2 87.0 °C/W
RθJC(top) Junction-to-case(top) thermal resistance(3) 46.2 44.4 °C/W
RθJB Junction-to-board thermal resistance(4) 58.9 41.7 °C/W
ψJT Junction-to-top characterization parameter(5) 4.9 11.6 °C/W
ψJB Junction-to-board characterization parameter(6) 58.3 41.4 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance(7) N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.8 Electrical Characteristics

VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V ±0.5 ±2.5 mV
VS = 5 V, TA = –40°C to 125°C ±3.5 mV
dVOS/dT Drift VS = 5 V, TA = –40°C to 125°C ±2 ±10 μV/°C
PSRR vs power supply VS = 1.8 V – 5.5 V, VCM = (V–) ±30 ±150 µV/V
VS = 1.8 V – 5.5 V, VCM = (V–), TA = –40°C to 125°C ±250 µV/V
Channel separation, dc At dc 10 µV/V
INPUT VOLTAGE RANGE
VCM Common-mode voltage VS = 1.8 V to 2.5 V (V–) – 0.2 (V+) V
VS = 2.5 V to 5.5 V (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VS = 1.8 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,
TA= –40°C to 125°C		 70 86 dB
VS = 5.5 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,
TA= –40°C to 125°C		 76 90 dB
VS = 1.8 V, VCM = –0.2 V to 1.8 V,
TA= –40°C to 125°C		 57 72 dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V,
TA= –40°C to 125°C		 65 80 dB
INPUT BIAS CURRENT
IB Input bias current ±5 ±15 pA
TA= –40°C to 125°C ±15 nA
IOS Input offset current ±2 ±15 pA
TA= –40°C to 125°C ±8 nA
NOISE
En Input voltage noise (peak-to-peak) VS = 5 V, f = 0.1 Hz to 10 Hz 3 μVPP
en Input voltage noise density VS = 5 V, f = 1 kHz 11 nV/√Hz
in Input current noise density f = 1 kHz 1.3 fA/√Hz
INPUT IMPEDANCE
ZID Differential 2 || 2 1016Ω || pF
ZIC Common-mode 2 || 4 1011Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ		 94 100 dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ		 104 110 dB
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 2 kΩ		 90 96 dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ		 100 106 dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ, TA= –40°C to 125°C		 86 dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ, TA= –40°C to 125°C		 84 dB
FREQUENCY RESPONSE
GBP Gain bandwidth product VS = 5 V, G = +1 10 MHz
φm Phase margin VS = 5 V, G = +1 60 Degrees
SR Slew rate VS = 5 V, G = +1 6 V/μs
tS Settling time To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF 1 μs
To 0.01%, VS = 5 V, 2-V step , G = +1, CL = 100 pF 1.66 μs
tOR Overload recovery time VS = 5 V, VIN  × gain = VS 0.3 μs
THD + N Total harmonic distortion + noise(1) VS = 5 V, VO = 0.5 VRMS, G = +1, f = 1 kHz 0.0008%
OUTPUT
VO Voltage output swing from supply rails VS = 1.8 V, RL = 10 kΩ, TA= –40°C to 125°C 15 mV
VS = 5.5 V, RL = 10 kΩ, TA= –40°C to 125°C 30 mV
VS = 1.8 V, RL = 2 kΩ, TA= –40°C to 125°C 60 mV
VS = 5.5 V, RL = 2 kΩ, TA= –40°C to 125°C 120 mV
ISC Short-circuit current VS = 5 V ±50 mA
ZO Open-loop output impedance VS = 5 V, f = 10 MHz 250 Ω
POWER SUPPLY
VS Specified voltage 1.8 5.5 V
IQ Quiescent current per amplifier VS = 5 V, IO = 0 mA, TA= –40°C to 125°C 400 500 µA
Power-on time VS = 0 V to 5.5 V 200 µs
SHUTDOWN (VS = 1.8 V to 5.5 V)(2)
IQSD Quiescent current, per device All amplifiers disabled, SHDN = VS– 0.01 1 µA
One amplifier disabled (OPA2316S) 345 µA
VIH High voltage (enabled) Amplifier enabled (V+) – 0.5 V
VIL Low voltage (disabled) Amplifier disabled (V–) + 0.2 V
tON Amplifier enable time(3) Full shutdown, G = 1, VOUT = 0.9 × VS / 2(4) 13 µs
Partial shutdown, G = 1, VOUT = 0.9 × VS / 2(4) 10 µs
tOFF Amplifier disable time(3) G = 1, VOUT = 0.1 × VS / 2 5 µs
SHDN pin input bias current (per pin) VIH = 5 V 3.5 pA
VIL = 0 V 2.5 pA
TEMPERATURE
Specified temperature –40 125 °C
TA Operating temperature –55 150 °C
Tstg Storage temperature –65 150 °C
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
(2) Ensured by design and characterization; not production tested.
(3) Enable time (tON) and disable time (tOFF) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(4) Full shutdown refers to the dual OPA2316S having both channels A and B disabled (SHDN_A = SHDN_B = VS–). For partial shutdown, only one SHDN pin is exercised; in partial mode, the internal biasing and oscillator remain operational and the enable time is shorter.

6.9 Typical Characteristics

at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
OPA316 OPA2316 OPA2316S OPA4316 C001_OT.png
Distribution taken from 12551 amplifiers
Figure 1. Offset Voltage Production Distribution
OPA316 OPA2316 OPA2316S OPA4316 C003_OT.png
9 typical units shown
Figure 3. Offset Voltage vs Temperature
OPA316 OPA2316 OPA2316S OPA4316 C005_OT.png
V+ = 0.9 V to 2.75 V, V– = –0.9 V to –2.75 V,
9 typical units shown
Figure 5. Offset Voltage vs Power Supply
OPA316 OPA2316 OPA2316S OPA4316 C022A_OT.png
RL = 10 kΩ
Figure 7. Open-Loop Gain vs Temperature
OPA316 OPA2316 OPA2316S OPA4316 C007_SBOS703.png
Figure 9. Closed-Loop Gain vs Frequency
OPA316 OPA2316 OPA2316S OPA4316 C010B_OT.png
V+ = 2.75 V, V– = –2.75 V
Figure 11. Output Voltage Swing vs Output Current
OPA316 OPA2316 OPA2316S OPA4316 C012A_OT.png
Figure 13. CMRR vs Temperature (Narrow Range)
OPA316 OPA2316 OPA2316S OPA4316 C013_OT.png
Figure 15. PSRR vs Temperature
OPA316 OPA2316 OPA2316S OPA4316 C015_SBOS703.png
Figure 17. Input Voltage Noise Spectral Density vs Frequency
OPA316 OPA2316 OPA2316S OPA4316 C017y_SBOS703.png
BW = 80 kHz, VOUT = 0.5 VRMS
Figure 19. THD + N vs Frequency
OPA316 OPA2316 OPA2316S OPA4316 C020_OT.png
Figure 21. Quiescent Current vs Supply Voltage
OPA316 OPA2316 OPA2316S OPA4316 C024_SBOS703.png
Figure 23. Open-Loop Output Impedance vs Frequency
OPA316 OPA2316 OPA2316S OPA4316 C026_SBOS703.png
V+ = 2.75 V, V– = –2.75 V , G = +1 V/V, RL = 1 kΩ
Figure 25. Small-Signal Overshoot vs Load Capacitance
OPA316 OPA2316 OPA2316S OPA4316 C028_SBOS703.png
V+ = 2.75 V, V– = –2.75 V , G = –10 V/V
Figure 27. Positive Overload Recovery
OPA316 OPA2316 OPA2316S OPA4316 C030_SBOS703.png
V+ = 2.75 V, V– = –2.75 V, G = +1 V/V
Figure 29. Small-Signal Step Response
OPA316 OPA2316 OPA2316S OPA4316 C032_SBOS703.png
CL = 100 pF, G = +1 V/V
Figure 31. Positive Large-Signal Settling Time
OPA316 OPA2316 OPA2316S OPA4316 C034_OT.png
Figure 33. Short-Circuit Current vs Temperature
OPA316 OPA2316 OPA2316S OPA4316 C036_SBOS703.png
PRF = –10 dBm
Figure 35. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR IN+) vs Frequency
OPA316 OPA2316 OPA2316S OPA4316 C002_OT.png
TA = –40°C to +125°C, Distribution taken from 70 amplifiers
Figure 2. Offset Voltage Drift Distribution
OPA316 OPA2316 OPA2316S OPA4316 C004_OT.png
V+ = 2.75 V, V– = –2.75 V, 9 typical units shown
Figure 4. Offset Voltage vs Common-Mode Voltage
OPA316 OPA2316 OPA2316S OPA4316 C006_SBOS703.png
VCM < (V+) – 1.4 V
Figure 6. Open-Loop Gain and Phase vs Frequency
OPA316 OPA2316 OPA2316S OPA4316 C022B_OT.png
RL = 2 kΩ
Figure 8. Open-Loop Gain vs Temperature
OPA316 OPA2316 OPA2316S OPA4316 C009_OT.png
Figure 10. Input Bias and Offset Current vs Temperature
OPA316 OPA2316 OPA2316S OPA4316 C011_SBOS703.png
Figure 12. CMRR and PSRR vs Frequency
(Referred to Input)
OPA316 OPA2316 OPA2316S OPA4316 C012B_OT.png
Figure 14. CMRR vs Temperature (Wide Range)
OPA316 OPA2316 OPA2316S OPA4316 C014_SBOS703.png
Figure 16. 0.1-Hz to 10-Hz Input Voltage Noise
OPA316 OPA2316 OPA2316S OPA4316 C039_SBOS703.png
ƒ = 1 kHz
Figure 18. Input Voltage Noise vs Common-Mode Voltage
OPA316 OPA2316 OPA2316S OPA4316 C018_SBOS703.png
ƒ = 1 kHz, BW = 80 kHz
Figure 20. THD + N vs Amplitude
OPA316 OPA2316 OPA2316S OPA4316 C021_OT.png
Figure 22. Quiescent Current vs Temperature
OPA316 OPA2316 OPA2316S OPA4316 C025_SBOS703.png
V+ = 2.75 V, V– = –2.75 V, G = –1 V/V
Figure 24. Small-Signal Overshoot vs Load Capacitance
OPA316 OPA2316 OPA2316S OPA4316 C027_SBOS703.png
V+ = 2.75 V, V– = –2.75 V
Figure 26. No Phase Reversal
OPA316 OPA2316 OPA2316S OPA4316 C029_SBOS703.png
V+ = 2.75 V, V– = –2.75 V, G = –10 V/V
Figure 28. Negative Overload Recovery
OPA316 OPA2316 OPA2316S OPA4316 C031_SBOS703.png
V+ = 2.75 V, V– = –2.75 V, CL = 100 pF, G = +1 V/V
Figure 30. Large-Signal Step Response
OPA316 OPA2316 OPA2316S OPA4316 C033_SBOS703.png
CL = 100 pF, G = +1 V/V
Figure 32. Negative Large-Signal Settling Time
OPA316 OPA2316 OPA2316S OPA4316 C035_SBOS703.png
Figure 34. Maximum Output Voltage vs
Frequency and Supply Voltage
OPA316 OPA2316 OPA2316S OPA4316 C00111_SBOS703.png
V+ = 2.75 V, V– = –2.75 V
Figure 36. Channel Separation vs Frequency