at
TA = 25°C, VS = 5.0 V, VCM = VS / 2,
RLOAD = 10 kΩ connected to VS / 2, and CL = 100
pF (unless otherwise noted)
Figure 5-1 Offset Voltage Distribution Figure 5-3 Offset Voltage vs Temperature Figure 5-5 Offset Voltage vs Common-Mode Voltage Figure 5-7 Open-Loop Gain and Phase vs Frequency
VS = 1.7 V, common-mode voltage
referenced to VS / 2 |
Figure 5-9 Input
Bias Current vs Common-Mode Voltage
VS = 5.5 V, common-mode voltage
referenced to VS / 2 |
Figure 5-11 Input
Bias Current vs Common-Mode VoltageFigure 5-13 Negative Input Bias Current Distribution Figure 5-15 Input
Bias Current vs Temperature Figure 5-17 Output Voltage Swing vs Output Current
(Maximum Supply) Figure 5-19 CMRR
vs Temperature Figure 5-21 0.1-Hz to 10-Hz Noise Figure 5-23 THD+N
Ratio vs Frequency Figure 5-25 Quiescent Current vs Supply Voltage Figure 5-27 Open-Loop Gain vs Temperature Figure 5-29 Small-Signal Overshoot vs Capacitive Load
(10-mV Step) Figure 5-31 No
Phase Reversal Figure 5-33 Negative Overload Recovery Figure 5-35 Small-Signal Step Response (10-mV Step) Figure 5-37 Large-Signal Step Response (4-V Step) Figure 5-39 Short-Circuit Current vs
Temperature Figure 5-41 EMIRR
vs Frequency
45
units, TA = –40°C to +125°C |
Figure 5-2 Offset Voltage Drift DistributionFigure 5-4 Offset Voltage vs Common-Mode Voltage Figure 5-6 Offset Voltage vs Supply Voltage Figure 5-8 Closed-Loop Gain and Phase vs Frequency
VS = 3.3 V, common-mode voltage
referenced to VS / 2 |
Figure 5-10 Input
Bias Current vs Common-Mode Voltage
VS = 5.5 V, common-mode voltage
referenced to VS / 2 |
Figure 5-12 Input
Bias Current vs Common-Mode VoltageFigure 5-14 Positive Input Bias Current Distribution Figure 5-16 Output Voltage Swing vs Output Current
(Maximum Supply) Figure 5-18 PSRR
vs Frequency Figure 5-20 PSRR
vs Temperature Figure 5-22 Input
Voltage Noise Spectral Density vs Frequency
f =
1 kHz, filter BW = 80 kHz |
Figure 5-24 THD+N
vs Output AmplitudeFigure 5-26 Quiescent Current vs Temperature Figure 5-28 Open-Loop Output Impedance vs Frequency Figure 5-30 Small-Signal Overshoot vs Capacitive Load
(10-mV Step) Figure 5-32 Positive Overload Recovery Figure 5-34 Small-Signal Step Response (10-mV Step) Figure 5-36 Large-Signal Step Response (4-V Step) Figure 5-38 Settling Time (1-V Positive Step) Figure 5-40 Maximum Output Voltage vs Frequency