SBOSA10F June 2021 – March 2024 OPA2992 , OPA4992 , OPA992
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | VCM = V– | ±0.21 | ±1 | mV | ||
TA = –40°C to 125°C | ±1.2 | ||||||
dVOS/dT | Input offset voltage drift | VCM = V– | TA = –40°C to 125°C | ±0.25 | µV/℃ | ||
PSRR | Input offset voltage versus power supply | OPA992, OPA2992, VCM = V–, VS = 5 V to 40 V | TA = –40°C to 125°C | ±0.2 | ±1.3 | μV/V | |
OPA2992SIRUGR, VCM = V–, VS = 5 V to 40 V | ±0.2 | ±3.7 | |||||
OPA4992, VCM = V–, VS = 5 V to 40 V | ±0.4 | ±1.8 | |||||
OPA992, OPA2992, OPA4992, VCM = V–, VS = 2.7 V to 40 V(1) | ±0.8 | ±7 | |||||
DC channel separation | 0.4 | µV/V | |||||
INPUT BIAS CURRENT | |||||||
IB | Input bias current | ±10 | pA | ||||
IOS | Input offset current | ±10 | pA | ||||
NOISE | |||||||
EN | Input voltage noise | f = 0.1 Hz to 10 Hz | 2.77 | μVPP | |||
0.49 | µVRMS | ||||||
eN | Input voltage noise density | f = 1 kHz | 7 | nV/√Hz | |||
f = 10 kHz | 4.4 | ||||||
iN | Input current noise density | f = 1 kHz | 60 | fA/√Hz | |||
INPUT VOLTAGE RANGE | |||||||
VCM | Common-mode voltage range | (V–) | (V+) | V | |||
CMRR | Common-mode rejection ratio | VS = 40 V, V– < VCM < (V+) – 2 V (PMOS pair) | TA = –40°C to 125°C | 100 | 115 | dB | |
VS = 5 V, V– < VCM < (V+) – 2 V (PMOS pair)(1) | 75 | 98 | |||||
VS = 2.7 V, V– < VCM < (V+) – 2 V (PMOS pair) | 90 | ||||||
VS = 2.7 – 40 V, (V+) – 1 V < VCM < V+ (NMOS pair) | 79 | ||||||
(V+) – 2 V < VCM < (V+) – 1 V | See Offset Voltage vs Common-Mode Voltage (Transition Region) | ||||||
INPUT IMPEDANCE | |||||||
ZID | Differential | 100 || 9 | MΩ || pF | ||||
ZICM | Common-mode | 6 || 1 | TΩ || pF | ||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | VS = 40 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V |
120 | 142 | dB | ||
VS = 40 V, VCM = VS / 2, (V–) + 0.12 V < VO < (V+) – 0.12 V |
TA = –40°C to 125°C | 142 | |||||
VS = 5 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V(1) |
104 | 125 | |||||
TA = –40°C to 125°C | 125 | ||||||
VS = 2.7 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V(1) |
90 | 105 | |||||
TA = –40°C to 125°C | 105 | ||||||
FREQUENCY RESPONSE | |||||||
GBW | Gain-bandwidth product | 10.6 | MHz | ||||
SR | Slew rate | VS = 40 V, G = +1, VSTEP = 10 V, CL = 20 pF(5) | 32 | V/μs | |||
tS | Settling time | To 0.1%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF | 0.65 | μs | |||
To 0.1%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF | 0.3 | ||||||
To 0.01%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF | 0.86 | ||||||
To 0.01%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF | 0.44 | ||||||
Phase margin | G = +1, RL = 10 kΩ, CL = 20 pF | 64 | ° | ||||
Overload recovery time | VIN × gain > VS | 170 | ns | ||||
THD+N | Total harmonic distortion + noise | VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ | 0.00005% | ||||
126 | dB | ||||||
VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω | 0.0032% | ||||||
90 | dB | ||||||
VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω | 0.00032% | ||||||
110 | dB | ||||||
OUTPUT | |||||||
Voltage output swing from rail | Positive and negative rail headroom |
VS = 40 V, RL = no load | 7 | mV | |||
VS = 40 V, RL = 10 kΩ | 48 | 60 | |||||
VS = 40 V, RL = 2 kΩ | 220 | 300 | |||||
VS = 2.7 V, RL = no load | 0.5 | ||||||
VS = 2.7 V, RL = 10 kΩ | 5 | 20 | |||||
VS = 2.7 V, RL = 2 kΩ | 20 | 50 | |||||
ISC | Short-circuit current | ±65(3) | mA | ||||
CLOAD | Capacitive load drive | See Phase Margin vs Capacitive Load | pF | ||||
ZO | Open-loop output impedance | IO = 0 A | See Open-Loop Output Impedance vs Frequency | Ω | |||
POWER SUPPLY | |||||||
IQ | Quiescent current per amplifier | OPA2992, OPA4992, IO = 0 A | 2.4 | 2.8 | mA | ||
TA = –40°C to 125°C | 2.84 | ||||||
OPA992, IO = 0 A | 2.48 | 2.92 | |||||
TA = –40°C to 125°C | 2.98 | ||||||
SHUTDOWN | |||||||
IQSD | Quiescent current per amplifier | VS = 2.7 V to 40 V, all amplifiers disabled, SHDN = V– + 2 V | 40 | 45 | µA | ||
ZSHDN | Output impedance during shutdown | VS = 2.7 V to 40 V, amplifier disabled | 10 || 2 | GΩ || pF | |||
VIH | Logic high threshold voltage (amplifier disabled) | For valid input high, the SHDN pin voltage should be greater than the maximum threshold but less than or equal to V+ or (V–) + 20 V, whichever is less | (V–) + 1.1 V |
V | |||
VIL | Logic low threshold voltage (amplifier enabled) | For valid input low, the SHDN pin voltage should be less than the minimum threshold but greater than or equal to V– | (V–) + 0.2 V |
V | |||
tON | Amplifier enable time (from shutdown) (2) | VS = ±20 V, G = +1, VCM = VS / 2, RL = 10 kΩ connected to V– | 5 | µs | |||
tOFF | Amplifier disable time (2) | VS = ±20 V, G = +1, VCM = VS / 2, RL = 10 kΩ connected to V– | 3 | µs | |||
SHDN pin input bias current (per pin) | VS = 2.7 V to 40 V, (V–) + 20 V (4) ≥ SHDN ≥ (V–) + 0.9 V | 500 | nA | ||||
VS = 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V | 400 |