SBOS070D
October 1997 – December 2019
OPA548
PRODUCTION DATA.
1
Features
2
Applications
Simplified Schematic
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Adjustable Current Limit
7.3.2
Enable/Status (E/S) Pin
7.3.3
Thermal Shutdown Status
7.4
Device Functional Modes
7.4.1
Output Disable
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Basic Circuit Connections
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Power Supply Requirements
8.2.1.2.2
Gain Setting and Input Configuration
8.2.1.2.3
Current Limit
8.2.1.2.4
Safe-Operating-Area
8.2.1.2.5
Heat Sinking
8.2.1.3
Application Curve
8.2.2
Monitoring Single- and Dual-Supplies
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Output Disable and Thermal Shutdown Status
8.2.3
Programmable Power Supply
8.3
System Examples
9
Power Supply Recommendations
9.1
Output Stage Compensation
9.2
Output Protection
10
Layout
10.1
Layout Guidelines
10.1.1
Safe Operating Area
10.1.2
Amplifier Mounting
10.1.3
Power Dissipation
10.1.4
Thermal Considerations
10.1.5
Heat Sinking
10.1.5.1
Heat Sink Selection Example
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Receiving Notification of Documentation Updates
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
KC|7
MSOT010
KTW|7
MPSF015
KVT|7
MPZF004
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbos070d_oa
sbos070d_pm
8.3
System Examples
Figure 33.
Switched Amplifier Schematic
Figure 34.
Multiple Current Limit Values Schematic
Figure 35.
Single Quadrant V × I Limiting
Figure 36.
Parallel Output for Increased Output Current Schematic