SBOS567A June 2011 – February 2024 OPA564-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Figure 8-12 shows two examples of generating the signal for VDIG. Figure 8-12(a) uses an 1N4732A zener to bias the VDIG to precisely 4.7V greater than V–. Figure 8-12(b) uses a high-voltage subregulator to derive the VDIG voltage. Ensure that any decoupling capacitance present on the VDIG pin does not cause a timing condition that violates the power-supply sequencing outlined in Section 8.3.