SBOS659C January   2022  – December 2022 OPA593

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Overcurrent Flag
      3. 7.3.3 Overtemperature Flag
      4. 7.3.4 Output Enable and Disable
      5. 7.3.5 Mux-Friendly Inputs
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Output Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 High Voltage 2:1 Multiplexer With Unity Gain
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at VS = 85 V, TA = 25°C, RL = 10 kΩ to mid-supply, IOUT limit set to 100 mA, and VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±20 ±100 µV
dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±0.4 ±2 µV/°C
PSRR Power supply rejection ratio VS = ±4 V to ±42.5 V 0.1 1 µV/V
INPUT BIAS CURRENT
IB Input bias current ±1 ±10 pA
TA = –40°C to +85°C ±350
TA = –40°C to +125°C ±5 nA
IOS Input offset current ±1 ±5 pA
TA = –40°C to +85°C ±250
TA = –40°C to +125°C ±1 nA
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 2.9 µVPP
en Input voltage noise density f = 10 Hz 75 nV/√Hz
f = 1 kHz 10
f = 10 kHz 7
in Current noise density f = 1 kHz 12 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage Linear operation (V–) – 0.1 (V+) – 3.5 V
CMRR Common-mode rejection (V–) ≤ VCM ≤ (V+) – 3.5 V 124 140 dB
TA = –40°C to +125°C 108 124
INPUT IMPEDANCE
Differential 1013 || 0.3 Ω || pF
Common-mode 1013 || 9.4 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ		 134 140 dB
TA = –40°C to +125°C 130 140
(V–) + 1 V < VO < (V+) – 1 V,
RL = 2 kΩ		 132 140
TA = –40°C to +125°C 130 135
(V–) + 2.5 V < VO < (V+) – 2.5 V,
RL = 600 Ω		 130 135
TA = –40°C to +125°C 125 130
FREQUENCY RESPONSE
GBW Gain-bandwidth product 10 MHz
SR Slew rate Gain = ±1, VOUT = 70-V step Rising 45 V/µs
Falling 35
tS Settling time To ±0.01%, gain = –1, VOUT = 70-V step, CL = 100 pF 2.9 µs
THD+N Total harmonic distortion + noise Gain = +1, VOUT = 70 VPP,
f = 1 kHz		 RL = 600 Ω –105 dB
RL = 2 kΩ –110
OUTPUT
VO Voltage output swing from rail RCL = 0 Ω connected to V– No load 10 25 mV
IOUT = 50 mA 50 125
IOUT = 100 mA 400 750
IOUT = 250 mA 1.2 2 V
Continuous output current, dc VS = 85 V, RCL = 2.29 kΩ, ILIMIT = 250 mA ±250 mA
CLOAD Capacitive load drive See typical curves pF
ZO Open-loop output impedance See typical curves Ω
Output impedance Output disabled, V– < VOUT < V+ 100 MΩ
Output capacitance Output disabled 56 pF
CURRENT LIMIT
ILIMIT Current limit ±25 ±250 mA
Current limit accuracy(3) Sourcing,
RL = 10 Ω to mid-supply		 ILIMIT = 25 mA,
VLIMIT =  3.33 V		 17 29 mA
ILIMIT = 50 mA,
VLIMIT =  2.98 V		 42 55
ILIMIT = 100 mA,
VLIMIT =  2.27V		 94 107
ILIMIT = 250 mA,
VLIMIT =  0.14 V		 237 263
Sinking,
RL = 10 Ω to mid-supply		 ILIMIT = 25 mA,
VLIMIT =  3.33 V		 10 45
ILIMIT = 50 mA,
VLIMIT =  2.98 V		 35 68
ILIMIT = 100 mA,
VLIMIT =  2.27 V		 85 115
ILIMIT = 250 mA,
VLIMIT =  0.14 V		 235 275
Current limit equation Resistor set, RCL connected between ILIMIT pin and V– (3.687 V × 4000) / (56.7 kΩ + RCL) mA
Voltage set, VLIMIT connected to ILIMIT pin and referenced to V– 4000 × (3.687 V – VLIMIT) / 56.7 kΩ
STATUS FLAG PIN (Referenced to E/D Com)
Status flag delay Overcurrent delay 10 µs
Overcurrent recovery delay 10
Thermal shutdown Alarm (status flag high) 170 °C
Return to normal operation (status flag low) 150
Status flag output voltage Normal operation See typical curves
E/D PIN
VE/D E/D voltage(1) Enable, pin open or forced high(2) E/D Com + 1.5 E/D Com + 5.5 V
Disable, pin forced low(2) E/D Com E/D Com + 0.5
IE/D E/D input current 50 µA
Output disable time 12 µs
Output enable time 18 µs
E/D COM PIN
E/D Com voltage (V–) (V+) – 6 V
POWER SUPPLY
IQ Quiescent current 3.25 3.75 mA
TA = –40°C to +125°C 4
Output disabled 0.25
(1) For information on the output enable and disable feature see Section 7.3.4.
(2) Enable and disable voltage thresholds can vary near the maximum temperature range; see Figure 6-67.
(3) Proper output swing headroom is necessary to maintain current limit accuracy; see Figure 6-19. to Figure 6-34.