SBOSA42 June   2024 OPA596

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Mux-Friendly Inputs
      2. 6.3.2 Thermal Protection
      3. 6.3.3 Slew Boost
      4. 6.3.4 Overload Recovery
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Bridge-Connected Piezoelectric Driver
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 DAC Output Gain and Buffer
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Single-Supply Piezoelectric Driver
      4. 7.2.4 High-Side Current Sense
      5. 7.2.5 High-Voltage Instrumentation Amplifier
      6. 7.2.6 Composite Amplifier
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)

5.5 Electrical Characteristics

at VS = 85V (±42.5V), TA = 25°C, RL = 10kΩ to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±0.2 ±1 mV
dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±1 ±6 µV/°C
PSRR Power supply rejection ratio 8V ≤ VS ≤ 85V ±1 ±5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±5 ±10 pA
TA = –40°C to +85°C ±50
TA = –40°C to +125°C ±1 nA
IOS Input offset current ±5 ±10 pA
TA = –40°C to +85°C ±50
TA = –40°C to +125°C ±1 nA
NOISE
Input voltage noise f = 0.1Hz to 10Hz 1.4 µVPP
en Input voltage noise density f = 100Hz 17.8 nV/√Hz
f = 1kHz 12.9
f = 10kHz 12.8
in Current noise density f = 1kHz 10 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage Linear operation (V–) – 0.1 (V+) – 3.5 V
CMRR Common-mode rejection (V–) ≤ VCM ≤ (V+) – 3.5V 126 140 dB
TA = –40°C to +125°C 124 140
INPUT IMPEDANCE
Differential 100 || 2.5 MΩ || pF
Common-mode 10 || 5.5 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 1V < VO < (V+) – 1.5V,
RL = 10kΩ to mid-supply		 134 140 dB
TA = –40°C to +125°C 120 140
(V–) + 3V < VO < (V+) – 3.5V,
RL = 2kΩ to mid-supply		 126
TA = –40°C to +125°C 126
FREQUENCY RESPONSE
GBW Gain-bandwidth product G = 1 2.25 MHz
G = 10 3
G = 100 3.75
SR Slew rate G = ±1, VO = 70V step 100 V/µs
tS Settling time To ±0.01%, G = –1, VO = 10V step, CL = 100pF 2 µs
Overload recovery G = –1 115 ns
THD+N Total harmonic distortion + noise G = +1, VO = 70VPP, f = 1kHz RL = 10kΩ –102 dB
RL = 2kΩ –95
OUTPUT
VO Voltage output swing from rail No load 12 50 mV
RL = 10kΩ to mid-supply 100 435
RL = 2kΩ to mid-supply 500 2.05 V
ISC Output current ±30 mA
CLOAD Capacitive load drive 1 nF
ZO Open-loop output impedance 550 Ω
CURRENT LIMIT
POWER SUPPLY
IQ Quiescent current IO = 0mA 420 490 µA
TA = –40°C to +125°C 500
TEMPERATURE
Overtemperature shutdown Shutdown temperature 185 °C
Thermal hysteresis 20