The balanced input stage of a wideband voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. Although the high-speed input stage does require relatively high input bias current (typically ±8 µA at each input terminal), the close matching can be used to reduce the output dc error caused by this current. The total output offset voltage can be considerably reduced by matching the dc source resistances appearing at the two inputs. This matching reduces the output dc error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 7-1, and using worst-case 25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to:

–(NG = noninverting signal gain)

±(NG × V_OS(MAX)) ± (R_F × I_OS(MAX))

= ±(2 × 4 mV) ± (402 Ω × 1 µA)

= ±8.4 mV

A fine-scale output offset null, or dc operating point adjustment, is often required. Numerous techniques are available for introducing dc offset control into an op-amp circuit. Most of these techniques eventually reduce to adding a dc current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input can be considered. However, the dc offset voltage on the summing junction sets up a dc current back into the source that must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a dc-coupled inverting amplifier, see Figure 8-5 for one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the dc offsetting current is brought into the inverting input node through resistor values that are much greater than the signal path resistors. This circuit configuration has minimal effect on the loop gain, and therefore, the frequency response.

Figure 8-5 DC-Coupled, Inverting Gain of –2 V/V, With Offset Adjustment