SBOS223H December   2001  – October 2024 OPA690

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics OPA690IDBV, VS = ±5 V
    6. 6.6  Electrical Characteristics OPA690IDBV, VS = 5 V
    7. 6.7  Electrical Characteristics OPA690ID, VS = ±5 V
    8. 6.8  Electrical Characteristics OPA690ID, VS = 5 V
    9. 6.9  Typical Characteristics: OPA690IDBV, VS = ±5V
    10. 6.10 Typical Characteristics: OPA690IDBV, VS = 5V
    11. 6.11 Typical Characteristics: OPA690ID, VS = ±5V
    12. 6.12 Typical Characteristics: OPA690ID, VS = 5V
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wideband Voltage-Feedback Operation
      2. 7.3.2 Input and ESD Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Operation
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bandwidth Versus Gain: Noninverting Operation
      2. 8.1.2 Inverting Amplifier Operation
      3. 8.1.3 Optimizing Resistor Values
      4. 8.1.4 Output Current and Voltage
      5. 8.1.5 Driving Capacitive Loads
      6. 8.1.6 Distortion Performance
      7. 8.1.7 Noise Performance
      8. 8.1.8 DC Accuracy and Offset Control
      9. 8.1.9 Thermal Analysis
    2. 8.2 Typical Applications
      1. 8.2.1 High-Performance DAC Transimpedance Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Single-Supply Active Filters
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curve
      3. 8.2.3 High-Power Line Driver
        1. 8.2.3.1 Design Requirements
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Macromodels and Applications Support
      2. 9.1.2 Demonstration Fixtures
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DBV|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Driving Capacitive Loads

One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that can be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA690 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series-isolation resistor between the amplifier output and the capacitive load. This configuration does not eliminate the pole from the loop response, but rather shifts the pole and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability.

The typical characteristics show the recommended RS versus capacitive load (Figure 6-51 for ±5 V and Figure 6-66 for 5 V), and the resulting frequency response at the load. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA690. Long PCB traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA690 output pin (see Section 8.4.1).

The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA690 operating in a gain of 2, the frequency response at the output pin is already slightly peaked without the capacitive load requiring relatively high values of RS to flatten the response at the load. Increasing the noise gain reduces the peaking as described previously. The circuit of Figure 8-2 demonstrates this technique, allowing lower values of RS to be used for a given capacitive load.

OPA690 Capacitive Load Driving With Noise Gain Tuning Figure 8-2 Capacitive Load Driving With Noise Gain Tuning

This gain of 2 V/V circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. Although this technique reduces the required RS resistor for a given capacitive load, this technique does increase the noise at the output. This technique also decreases the loop gain, slightly decreasing the distortion performance. If, however, the dominant distortion mechanism arises from a high RS value, significant dynamic range improvement can be achieved using this technique. Figure 8-3 shows the required RS versus CLOAD parametric on noise gain using this technique. This is the circuit of Figure 8-2 with RNG adjusted to increase the noise gain (increasing the phase margin) then sweeping CLOAD and finding the required RS to get a flat frequency response. This plot also gives the required RS versus CLOAD for the OPA690 operated at higher signal gains.

OPA690 Required
                        RS vs Noise Gain Figure 8-3 Required RS vs Noise Gain