One of the most demanding, and yet very common, load conditions for an operational amplifier is capacitive loading. Often, the capacitive load is the input of an ADC, including additional external capacitance that can be recommended to improve ADC linearity. A high-speed, high-open-loop-gain amplifier like the OPA695 can be susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the open-loop output resistance of the amplifier is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the simplest and most effective solution is to isolate the capacitive load (C_L) from the feedback loop by inserting a series isolation resistor (R_ISO) between the amplifier output and the capacitive load. Figure 7-3 shows this configuration. This configuration does not eliminate the pole from the loop response, but shifts the pole and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability.

Figure 7-3 Driving a Large Capacitive Load Using an Output Series Isolation Resistor

The Typical Characteristics show the recommended R_S versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA695. Long PCB traces, unmatched cables, and connections to multiple devices can exceed this value. Always consider this effect carefully and add the recommended series resistor as close as possible to the OPA695 output pin (see Section 7.4.1).