SBOSA14A April   2023  – November 2023 OPA814

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics:
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 FET-Input Architecture With Wide Gain-Bandwidth Product
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Wideband, High-Input Impedance DAQ Front-End
      2. 8.1.2 Wideband, Transimpedance Design Using the OPA814
    2. 8.2 Typical Application
      1. 8.2.1 High-Input-Impedance, 180-MHz, Digitizer Front-End Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics:

at TA ≅ 25°C, VS = ±5 V, G = 1 V/V, RF = 0 Ω, RF = 250 Ω for G ≥ 2 V/V, RL = 100 Ω, and input and output referenced to mid-supply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 200 mVPP, G = 1 V/V 600 MHz
VOUT = 200 mVPP, G = 2 V/V 250
VOUT = 200 mVPP, G = 10 V/V 25
Gain-bandwidth product G >= 10 V/V 250 MHz
LSBW Large-signal bandwidth VOUT = 2 VPP, G = 1 V/V 200 MHz
VOUT = 2 VPP, G = 2 V/V 165
VOUT = 4 VPP, G = 1 V/V 110
Bandwidth for 0.1-dB flatness VOUT = 2 VPP 70 MHz
Peaking at G = 1 V/V VOUT = 200 mVPP 0.6 dB
SR Slew rate VOUT = 1-V step, G = 2 V/V 550 V/µs
VOUT = 4-V step, G = 1 V/V 750
tR, tF Rise, fall time VOUT = 200-mV step, G = 1 V/V, 10%–90% 0.8 ns
VOUT = 200-mV step, G = 2 V/V, 10%–90% 1.3
Settling time to 0.1% VOUT = 2-V step, G = 1 V/V 7 ns
Settling time to 0.02% VOUT = 2-V step, G = 2 V/V 16 ns
Overshoot VOUT = 2-V step 6 %
Undershoot VOUT = 2-V step 10 %
Output overdrive recovery time VIN = ±2.5 V, G = 2 V/V 30 ns
HD2 Second-order harmonic distortion f = 1 MHz, VOUT = 2 VPP, RL = 1 kΩ –119 dBc
HD3 Third-order harmonic distortion –130
HD2 Second-order harmonic distortion f = 10 MHz, VOUT = 2 VPP, RL = 100 Ω –75 dBc
HD3 Third-order harmonic distortion –85
eN Input voltage noise f > 100 kHz 5.3 nV/√Hz
Voltage noise 1/f corner frequency 2 kHz
Input current noise f > 100 kHz 11 fA/√Hz
DC PERFORMANCE
AOL Open-loop voltage gain VO = ±0.5 V 75 80 dB
VO = ±0.5 V, TA = –40°C to +85°C 70
VOS Input-referred offset voltage SOIC 50 ±250 µV
SOIC, TA = –40°C to +85°C ±500
SOT-23 100 ±350
SOT-23, TA = –40°C to +85°C ±600
Input offset voltage drift(1) TA = –40°C to +85°C 1 ±3.5 µV/°C
IB Input bias current 2 ±20 pA
TA = –40°C to +85°C ±1000
IOS Input offset current 1 ±20 pA
TA = –40°C to +85°C ±500
INPUT
CMIR Most positive input voltage CMRR > 77 dB 2.1 2.7 V
TA = –40°C to +85°C, CMRR > 77 dB 2
CMRR > 53 dB 2.6 3.1
TA = –40°C to +85°C, CMRR > 53 dB 2.4
Most negative input voltage CMRR > 77 dB –4.3 –3.9 V
TA = –40°C to +85°C, CMRR > 77 dB –3.7
CMRR > 53 dB –4.4 –4
TA = –40°C to +85°C, CMRR > 53 dB –3.8
CMRR Common-mode rejection ratio VCM = ±0.5 V 84 100 dB
VCM = ±0.5 V, TA = –40 to +85°C 83
Input impedance common-mode 12 || 2.5 GΩ || pF
Input impedance differential mode 1000 || 0.2 GΩ || pF
OUTPUT

Voltage output swing
 		 No load ±3.7 ±3.9 V
SOIC, RL = 100 Ω ±3.4 ±3.7
SOT-23, RL = 100 Ω ±3.35 ±3.7
TA = –40°C to +85°C, RL = 100 Ω ±3.3
Linear output drive
(sourcing and sinking)		 VOUT = ±1 V, ΔVOS < 2 mV 52 70 mA
TA = –40 to +85°C,
VOUT = ±1 V, ΔVOS < 3 mV		 45
Short-circuit current 90 mA
ZO Closed loop output Impedance f = 100 kHz, G = 1 V/V 0.01 Ω
POWER SUPPLY
IQ Quiescent current 15.3 16 16.7 mA
TA = –40°C to +85°C 15.2 16.8
PSRR+ Power-supply rejection ratio
(positive)		 SOIC, VS+ = 4.5 V to 5.5 V 79 100 dB
SOIC, VS+ = 4.5 V to 5.5 V, 
TA = –40°C to +85°C		 76
SOT-23, VS+ = 4.5 V to 5.5 V 77 100
SOT-23, VS+ = 4.5 V to 5.5 V, 
TA = –40°C to +85°C		 74
PSRR– Power-supply rejection ratio
(negative)		 SOIC, VS– = –4.5 V to –5.5 V 79 100 dB
SOIC, VS– = –4.5 V to –5.5 V, 
TA = –40°C to +85°C		 76
SOT-23, VS– = –4.5 V to –5.5 V 77 100
SOT-23, VS– = –4.5 V to –5.5 V, 
TA = –40°C to +85°C		 74
(1) Based on electrical characterization of 32 devices. Minimum and maximum values are not specified by final automated test equipment (ATE) nor by QA sample testing. Typical specifications are ±1 sigma.