SBOS847B July   2022  – December 2024 OPA817

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: VS = ±5 V
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 Feedback Pin
      3. 7.3.3 FET-Input Architecture With Wide Gain-Bandwidth Product
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down (PD) Pin
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Wideband, High-Input-Impedance DAQ Front End
    2. 8.2 Typical Applications
      1. 8.2.1 High-Input-Impedance, 200-MHz, Digitizer Front-End Amplifier Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DTK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

FET-Input Architecture With Wide Gain-Bandwidth Product

Figure 7-5 shows the open-loop gain and phase response of the OPA817. The GBWP of an op amp is measured in the 20-dB/decade constant slope region of the AOL magnitude plot. The open-loop gain of 60 dB for the OPA817 is along this 20-dB/decade slope, and the corresponding frequency intercept is at 400 kHz. Converting 60 dB to linear units (1000 V/V) and multiplying by the 400-kHz frequency intercept gives a GBWP of 400 MHz for the OPA817. The AOL Bode plot shows that the second pole in the AOL response occurs after AOL magnitude drops to less than 0 dB (1 V/V). The location of second pole results in phase change of less than 180° at 0 dB AOL, indicating that the amplifier is stable in a gain of 1 V/V. Amplifiers such as the OPA817 that are JFET-input, low noise and unity-gain stable can be used as high-input-impedance buffers and gain stages with minimal degradation in SNR. The device has 800 MHz of SSBW in a gain-of-1-V/V configuration with a phase margin of approximately 55°.

The low input offset voltage and offset voltage drift of OPA817 makes the device an excellent amplifier for high-precision, high-input-impedance, wideband, data-acquisition-system front-ends. Figure 8-2 shows that the system benefits from the low noise JFET input stage with pico-amperes of input bias current to achieve higher precision at 1-MΩ input impedance setting and higher SNR at 50-Ω input impedance setting simultaneously in a typical data-acquisition front-end circuit.

OPA817 Open-Loop Gain Magnitude
                        and Phase vs Frequency
RL = 100 Ω
Figure 7-5 Open-Loop Gain Magnitude and Phase vs Frequency
OPA817 Open-Loop Gain Magnitude
                        vs Temperature
RL = 100 Ω
Figure 7-6 Open-Loop Gain Magnitude vs Temperature