SBOS847A July   2022  – December 2022 OPA817

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = ±5 V
    6. 7.6 Typical Characteristics: VS = ±5 V
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and ESD Protection
      2. 8.3.2 Feedback Pin
      3. 8.3.3 FET-Input Architecture with Wide Gain-Bandwidth Product
      4. 8.3.4 Device Functional Modes
        1. 8.3.4.1 Power-Down (PD) Pin
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Wideband, High-Input Impedance DAQ Front-End
    2. 9.2 Typical Applications
      1. 9.2.1 High Input Impedance, 200 MHz, Digitizer Front-End Amplifier Design
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

FET-Input Architecture with Wide Gain-Bandwidth Product

Figure 8-5 shows the open-loop gain and phase response of the OPA817. The GBWP of an op amp is measured in the 20 dB/decade constant slope region of the AOL magnitude plot. The open-loop gain of 60 dB for the OPA817 is along this 20 dB/decade slope and the corresponding frequency intercept is at 400 kHz. Converting 60 dB to linear units (1000 V/V) and multiplying it with the 400 kHz frequency intercept gives the GBWP of OPA817 as 400 MHz. As can be inferred from the AOL Bode plot, the second pole in the AOL response occurs after AOL magnitude drops below 0 dB (1 V/V). This results in phase change of less than 180° at 0 dB AOL indicating that the amplifier will be stable in a gain of 1 V/V. Amplifiers like OPA817 that are JFET-input, low noise and unity-gain stable can be used as high input impedance buffers and gain stages with minimal degradation in SNR. It has 800 MHz of SSBW in gain of 1V/V configuration with approximately 55° phase margin.

The low input offset voltage and offset voltage drift of OPA817 makes it a very suitable amplifier for high precision, high input impedance, wideband data acquisition system front-ends. As Figure 9-2 shows, the system benefits from the low noise JFET input stage with pico-amperes of input bias current to achieve higher precision at 1-MΩ input impedance settings and higher SNR at 50-Ω input impedance setting simultaneously in a typical data acquisition front-end circuit.

RL = 100 Ω
Figure 8-5 Open-Loop Gain Magnitude and Phase Vs Frequency
RL = 100 Ω
Figure 8-6 Open-Loop Gain Magnitude vs Temperature