SBOS673D September   2017  – December 2018 OPA2837 , OPA837

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Low-Power, Low-Noise, Precision, Single-Ended SAR ADC Driver With True Ground Input and Output Range
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: OPA837
    5. 6.5  Thermal Information: OPA2837
    6. 6.6  Electrical Characteristics: VS = 5 V
    7. 6.7  Electrical Characteristics: VS = 3 V
    8. 6.8  Typical Characteristics: VS = 5.0 V
    9. 6.9  Typical Characteristics: VS = 3.0 V
    10. 6.10 Typical Characteristics: ±2.5-V to ±1.5-V Split Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 OPA837 Comparison
      2. 7.3.2 Input Common-Mode Voltage Range
      3. 7.3.3 Output Voltage Range
      4. 7.3.4 Power-Down Operation
      5. 7.3.5 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      6. 7.3.6 Driving Capacitive Loads
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2 Single-Supply Operation (2.7 V to 5.4 V)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Noninverting Amplifier
      2. 8.1.2  Inverting Amplifier
      3. 8.1.3  Output DC Error Calculations
      4. 8.1.4  Output Noise Calculations
      5. 8.1.5  Instrumentation Amplifier
      6. 8.1.6  Attenuators
      7. 8.1.7  Differential to Single-Ended Amplifier
      8. 8.1.8  Differential-to-Differential Amplifier
      9. 8.1.9  Pulse Application With Single-Supply Circuit
      10. 8.1.10 ADC Driver Performance
    2. 8.2 Typical Applications
      1. 8.2.1 Active Filters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Implementing a 2:1 Active Multiplexer
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 1-Bit PGA Operation
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics: VS = 5 V

at VS+ = 5 V, VS– = 0 V, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output referenced to mid-supply, and TA ≈ 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1 90 105 MHz C
VOUT = 20 mVPP, G = 2 45 C
VOUT = 20 mVPP, G = 10 5 C
GBP Gain-bandwidth product VOUT = 20 mVPP, G = 10 45 50 MHz C
LSBW Large-signal bandwidth VOUT = 2 VPP, G = 2 26 MHz C
Bandwidth for 0.1-dB flatness VOUT = 200 mVPP, G = 2 6 MHz C
SR Slew rate From  LSBW(2) 105 V/µs C
tR, tF Rise, fall time VOUT = 0.5-V step, G = 2, input tR = 10 ns 10 11 ns C
Overshoot VOUT = 2-V step, G = 2, input tR = 40 ns 7.0% C
Settling time to 0.1% VOUT = 2.0-V step, G = 1, input tR = 4 ns 25 ns C
Settling time to 0.01% VOUT = 2.0-V step, G = 1, input tR = 4 ns 40 ns C
HD2 Second-order harmonic distortion f = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73) –120 dBc C
HD3 Third-order harmonic distortion f = 100 kHz, VO = 2 VPP, G = 1 (see Figure 73) –145 dBc C
Input voltage noise f = 500 Hz 4.7 nV/√Hz C
Voltage noise 1/f corner frequency See Figure 39 35 Hz C
Input current noise f = 20 kHz 0.4 pA/√Hz C
Current noise 1/f corner frequency See Figure 39 5 kHz C
Overdrive recovery time G = 2, 2x output overdrive (see Figure 30) 75 ns C
Closed-loop output impedance f = 1 MHz, G = 1 (see Figure 38) 0.14 Ω C
Channel-to-channel crosstalk (OPA2837) f = 10 kHz -126 dBc C
DC PERFORMANCE
AOL Open-loop voltage gain VO = ±2 V, RL = 2 kΩ 120 135 dB A
Input-referred offset voltage TA ≈ 25°C  –165 ±30 165 µV A
TA = 0°C to +70°C (DCK package) –205 ±30 235 B
TA = –40°C to +85°C (DCK package) –269 ±30 261 B
TA = –40°C to +125°C (DCK package) –269 ±30 325 B
Input offset voltage drift(4) DCK package, TA = –40°C to +125°C –1.6 ±0.4 1.6 µV/°C B
DBV, RUN package, TA = –40°C to +125°C –2.0 ±0.4 2.0 B
DGK package, TA = –40°C to +125°C ±0.67 B
Input bias current(3) TA ≈ 25°C 150 340 520 nA A
TA = 0°C to +70°C 50 340 664 B
TA = –40°C to +85°C 50 340 718 B
TA = –40°C to +125°C 50 340 850 B
Input bias current drift(4) TA = –40°C to +125°C 0.8 1.5 3.3 nA/°C B
Input offset current TA ≈ 25°C (OPA837) –40 ±6 40 nA A
TA = 0°C to +70°C –46 ±6 52 B
TA = –40°C to +85°C –56 ±6 55 B
TA = –40°C to +125°C –56 ±6 65 B
TA ≈ 25°C (OPA2837) -60 ±8 60 A
Input offset current drift(4) TA = –40°C to +125°C –250 ±40 250 pA/°C B
TA = –40°C to +125°C (OPA2837) –270 ±80 330 B
Input-referred offset voltage mismatch TA ≈ 25°C (OPA2837) -220 50 220 µV A
INPUT
Common-mode input range, low TA ≈ 25°C, < 3-dB degradation in CMRR limit –0.2 0 V A
TA = –40°C to +125°C, < 3-dB degradation in CMRR limit –0.2 0 B
Common-mode input range, high TA ≈ 25°C, < 3-dB degradation in CMRR limit 3.7 3.8 V A
TA = –40°C to +125°C, < 3-dB degradation in CMRR limit 3.7 3.8 B
CMRR Common-mode rejection ratio 91 110 dB A
Input impedance common-mode 175 || 1.5 MΩ || pF C
Input impedance differential mode 180 || 0.5 kΩ || pF C
OUTPUT
VOL Output voltage, low TA ≈ 25°C, G = 2 0.05 0.1 V A
TA = –40°C to +125°C, G = 5 0.05 0.1 B
VOH Output voltage, high TA ≈ 25°C, G = 2 4.9 4.95 V A
TA = –40°C to +125°C, G = 5 4.8 4.9 B
Maximum current into a resistive load TA ≈ 25°C, ±1.6 V into 27 Ω, VIO < 2 mV ±58 ±70 mA A
Linear current into a resistive load TA ≈ 25°C, ±1.7 V into 37.4 Ω, AOL > 80 dB ±45 ±50 mA A
Linear current into a resistive load overtemperature TA = –40°C to +125°C, ±1.31 V into 37.4 Ω, AOL > 80 dB ±35 ±45 mA C
Closed-loop output impedance Gain of 1 V/V, ±30-mA DC 0.6 mΩ C
POWER SUPPLY
Specified operating voltage 2.7 5.4 V B
Quiescent operating current per amplifier (5-V supply) TA ≈ 25°C(5) 564 592 625 µA A
TA = –40°C to +125°C 408 592 865 B
Supply current temperature coefficient per amplifier TA = –40°C to +125°C (see Figure 57) 1.1 1.9 2.4 µA/°C B
+PSRR Positive power-supply rejection ratio 95 110 dB A
–PSRR Negative power-supply rejection ratio 92 108 dB A
POWER DOWN (Pin Must be Driven)
Enable voltage threshold Specified on above VS– + 1.5 V 1.5 V A
Disable voltage threshold Specified off below VS– + 0.55 V 0.55 V A
Power-down pin bias current PD = 0 V to VS+ –50 50 nA A
Power-down quiescent current PD ≤ 0.55 V 4 5 10 µA A
Power-down quiescent current over temperature PD ≤ 0.55 V, TA = –40°C to +125°C 10 µA B
Turnon time delay Time from PD = high to VOUT = 90% of final value 300 ns C
Turnoff time delay Time from PD = low to VOUT = 10% of original value 100 ns C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB where this f–3dB is the typical measured 2-VPP bandwidth at gains of 1 V/V.
(3) Current is considered positive out of the pin.
(4) Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end points, computing the difference, and dividing by the temperature range. Typical drift specifications are ±1sigma. Maximum drift specifications are set by min/max sample packaged test data using a wafer-level screened drift. Min/Max drift is not specified by final automated test equipment (ATE) nor by QA sample testing.
(5) The typical specification is at 25°C TJ. The min, max limits are expanded for the automated test equipment (ATE) to account for an ambient range from 22°C to 32°C with a 2-µA/°C temperature coefficient on the supply current.