SBOSA57B February   2021  – January 2023 OPA855-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input and ESD Protection
      2. 9.3.2 Feedback Pin
      3. 9.3.3 Wide Gain-Bandwidth Product
      4. 9.3.4 Slew Rate and Output Stage
    4. 9.4 Device Functional Modes
      1. 9.4.1 Split-Supply and Single-Supply Operation
      2. 9.4.2 Power-Down Mode
  10. 10Application, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure
      3. 10.3.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.2 Power-Down Mode

The OPA855-Q1 features a power-down mode to reduce the quiescent current to conserve power. Figure 7-23 and Figure 7-24 show the transient response of the OPA855-Q1 as the PD pin toggles between the disabled and enabled states.

The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65 V supplies, then the threshold voltages are at –1 V and 0.15 V. If the amplifier is configured with ±2.5 V supplies, then the threshold voltages are at –1.85 V and –0.7 V.

Figure 9-8 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled state to the disabled state. Similarly, Figure 9-9 shows the switching behavior of a typical amplifier as the PD pin is swept up from the disabled state to the enabled state. The small difference in the switching thresholds between the down sweep and the up sweep is caused by the hysteresis designed into the amplifier to increase immunity to noise on the PD pin.

GUID-570DB1AE-EF30-4FB3-8897-68140C76970B-low.gifFigure 9-8 Switching Threshold
(PD Pin Swept from High to Low)
GUID-741431A6-8538-4E8D-A141-C7B303C93181-low.gifFigure 9-9 Switching Threshold ( PD Pin Swept from Low to High)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA855-Q1 uses internal, back-to-back protection diodes between the inverting and noninverting input pins as Figure 9-3 shows. In the power-down state, if the differential voltage between the input pins of the amplifier exceeds a diode voltage drop, an additional low-impedance path is created between the noninverting input pin and the output pin.