SBOSA57B February   2021  – January 2023 OPA855-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input and ESD Protection
      2. 9.3.2 Feedback Pin
      3. 9.3.3 Wide Gain-Bandwidth Product
      4. 9.3.4 Slew Rate and Output Stage
    4. 9.4 Device Functional Modes
      1. 9.4.1 Split-Supply and Single-Supply Operation
      2. 9.4.2 Power-Down Mode
  10. 10Application, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure
      3. 10.3.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

at VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 100 mVPP 2.5 GHz
LSBW Large-signal bandwidth VOUT = 2 VPP 850 MHz
GBWP Gain-bandwidth product 8 GHz
Bandwdith for 0.1-dB flatness 200 MHz
SR Slew rate (10%-90%) VOUT = 2-V step 2750 V/µs
tr Rise time VOUT = 100-mV step 0.17 ns
tf Fall time VOUT = 100-mV step 0.17 ns
Settling time to 0.1% VOUT = 2-V step 2.3 ns
Settling time to 0.001% VOUT = 2-V step 2600 ns
Overshoot or undershoot VOUT = 2-V step 5%
Overdrive recovery 2x output overdrive 3 ns
HD2 Second-order harmonic distortion f = 10 MHz, VOUT = 2 VPP 90 dBc
f = 100 MHz, VOUT = 2 VPP 65
HD3 Third-order harmonic distortion f = 10 MHz, VOUT = 2 VPP 86 dBc
f = 100 MHz, VOUT = 2 VPP 74
en Input-referred voltage noise f = 1 MHz 0.98 nV/√Hz
ei Input-referred current noise f = 1 MHz 2.5 pA/√Hz
zO Closed-loop output impedance f = 1 MHz 0.15 Ω
DC PERFORMANCE
AOL Open-loop voltage gain 70 76 dB
VOS Input offset voltage TA = 25°C –1.5 ±0.2 1.5 mV
ΔVOS/ΔT Input offset voltage drift TA = –40°C to 125°C 0.5 µV/°C
IB Input bias current (1) TA = 25°C –20 –12 –5 µA
ΔIB/ΔT Input bias current drift TA = –40°C to +125°C –0.08 µA/°C
IBOS Input offset current TA = 25°C –1 ±0.1 1 µA
ΔIBOS/ΔT Input offset current drift TA = –40°C to +125°C 1 nA/°C
CMRR Common-mode rejection ratio VCM = ±0.5 V referred to midsupply 90 100 dB
INPUT
Common-mode input resistance 2.3 MΩ
CCM Common-mode input capacitance 0.6 pF
Differential input resistance 5 kΩ
CDIFF Differential input capacitance 0.2 pF
VIH Common-mode input range (high) CMRR > 80 dB, VS+ = 3.3 V 2.7 2.9 V
VIL Common-mode input range (low) CMRR > 80 dB, VS+ = 3.3 V 1.1 1.3 V
VIH Common-mode input range (high) CMRR > 80 dB 4.4 4.6 V
VIH Common-mode input range (high) TA = –40°C to +125 °C, CMRR > 80 dB 4.3 V
VIL Common-mode input range (low) CMRR > 80 dB 1.1 1.3 V
VIL Common-mode input range (low) TA = –40°C to +125°C, CMRR > 80 dB 1.3 V
OUTPUT
VOH Output voltage (high)(2) TA = 25°C, VS+ = 3.3 V 2.35 2.4 V
VOH Output voltage (high)(2) TA = 25°C 3.95 4.1 V
TA = –40°C to +125°C 4
VOL Output voltage (low)(2) TA = 25°C, VS+ = 3.3 V 1.05 1.15 V
VOL Output voltage (low)(2) TA = 25°C 1.05 1.15 V
TA = –40°C to +125°C 1.1
IO_LIN Linear output drive (sink and source) RL = 10 Ω, AOL > 60 dB 65 80 mA
TA = –40°C to +125°C, RL = 10 Ω, AOL > 60 dB 70
ISC Output short-circuit current 85 105 mA
POWER SUPPLY
IQ Quiescent current 16 17.8 19.5 mA
TA = –40°C 16.7
TA = 125°C 19.5
PSRR+ Positive power-supply rejection ratio 80 86 dB
PSRR– Negative power-supply rejection ratio 70 80
POWER DOWN
Disable voltage threshold Amplifier OFF below this voltage 0.65 1 V
Enable voltage threshold Amplifier ON below this voltage 1.5 1.8 V
Power-down quiescent current 70 140 μA
PD bias current 70 140 μA
Turnon time delay Time to VOUT = 90% of final value 15 ns
Turnoff time delay 120 ns
(1) Current flowing into the input pin is considered negative
(2) Amplifier output saturated