SBOSA95F May   2022  – October 2024 OPA2863A , OPA863A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information OPA863A
    5. 6.5  Thermal Information OPA2863A
    6. 6.6  Electrical Characteristics VS = ±5 V
    7. 6.7  Electrical Characteristics VS = 3 V
    8. 6.8  Typical Characteristics: VS = ±5 V
    9. 6.9  Typical Characteristics: VS = 3 V
    10. 6.10 Typical Characteristics: VS = 3 V to 10 V
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stage
      2. 7.3.2 Output Stage
        1. 7.3.2.1 Overload Power Limit
      3. 7.3.3 ESD Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Active Filters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Power SAR ADC Driver and Reference Buffer
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Input Stage

The OPAx863A include a rail-to-rail input stage. The main stage differential pair using PNP bipolar transistors operates for common-mode input voltages from VS– – 0.2 V to VS+ – 1.6 V. The amplifier inputs transition into the auxiliary stage using NPN transistors for common-mode input voltages from VS+ – 1.6 V till VS+ + 0.2 V. The PNP and NPN input stages offer a gain-bandwidth product of 50 MHz and a voltage noise density of 6.3 nV/√Hz. The offset voltage for the two input stages is matched to lie within the device specifications. The auxiliary NPN input stage does not use the slew-boost circuit during large-signal transient response. The input bias current for the PNP and NPN input stages is opposite in polarity, which adds an additional offset based on the values of the gain-setting and feedback resistors. A common-mode input voltage transition between these input stages causes a crossover distortion that must be considered in high-frequency applications requiring excellent linearity. Limit the common-mode input voltage to VS+ – 1.6 V (maximum) for main-stage operation across process and ambient temperature.

The OPAx863A are bipolar amplifiers; therefore, the two inputs are protected with antiparallel back-to-back diodes between the inputs, which limits the maximum input differential voltage to 1 V. The amplifier is slew limited, and the two inputs are pulled apart up to 1 V when the antiparallel diodes begin to conduct in very fast input or output transient conditions. Make sure to use gain-setting and feedback resistors large enough to limit the current through these diodes in such conditions.