SBOSAF2C June   2023  – September 2024 OPA2994 , OPA994

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Unlimited Capacitive Load Drive
      2. 6.3.2 Common-Mode Voltage Range
      3. 6.3.3 Phase Reversal Protection
      4. 6.3.4 Electrical Overstress
      5. 6.3.5 Overload Recovery
      6. 6.3.6 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DBV|5
  • DCK|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

For VS = (V+) – (V–) = 2.7V to 32V (±1.35V to ±16V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.35 ±2.3 mV
TA = –40°C to 125°C ±3.3
dVOS/dT Input offset voltage drift VCM = V– TA = –40°C to 125°C ±2.5 µV/℃
PSRR Input offset voltage versus power supply VCM = V–, VS = 5V to 32V TA = –40°C to 125°C ±3.5 ±22 μV/V
VCM = V–, VS = 2.7V to 32V TA = –40°C to 125°C ±60(1) μV/V
DC channel separation 1 µV/V
INPUT BIAS CURRENT
IB Input bias current ±400 ±1500 nA
IOS Input offset current ±7 nA
NOISE
EN Input voltage noise f = 0.1Hz to 10Hz   1.8 μVPP
  0.3   µVRMS
eN Input voltage noise density f = 1kHz 12   nV/√Hz
f = 10kHz   11  
iN Input current noise density f = 1kHz   1   pA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode input voltage range (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = 32V, V– < VCM < (V+) – 2V
(Main Input Pair)		 TA = –40°C to 125°C 109 125 dB
VS = 5V, V– < VCM < (V+) – 2V
(Main Input Pair)(1)		 TA = –40°C to 125°C 93 111
VS = 2.7V, V– < VCM < (V+) – 2V
(Main Input Pair)		 TA = –40°C to 125°C 114
VS = 2.7 – 32V, (V+) – 1V < VCM < V+
(Aux Input Pair)		 TA = –40°C to 125°C 77
(V+) – 2V < VCM < (V+) – 1V TA = –40°C to 125°C See Offset Voltage vs Common-Mode Voltage (Transition Region)
INPUT IMPEDANCE
ZID Differential 0.2 || 1 MΩ || pF
ZICM Common-mode 2 || 0.5 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 32V, VCM = VS / 2,
(V–) + 1V < VO < (V+) –  1V		 80 87 dB
TA = –40°C to 125°C 87
VS = 5V, VCM = VS / 2,
(V–) + 1V < VO < (V+) –  1V(1)		 75 80
TA = –40°C to 125°C 80
VS = 2.7V, VCM = VS / 2,
(V–) + 1V < VO < (V+) –  1V(1)		 75 80
TA = –40°C to 125°C 80
FREQUENCY RESPONSE
GBW Gain-bandwidth product 24 MHz
SR Slew rate VS = 32V, VSTEP = 10V, G = +1, CL = 20pF 35 V/μs
tS Settling time To 0.1%, VS = 32V, VSTEP = 10V, G = +1, CL = 50pF 0.43 µs
To 0.1%, VS = 32V, VSTEP = 10V, G = +1, CL = 500pF 0.45
To 0.01%, VS = 32V, VSTEP = 10V, G = +1, CL = 50pF 0.77
To 0.01%, VS = 32V, VSTEP = 10V, G = +1, CL = 500pF 0.85
Phase margin G = +1, RL = 10kΩ, CL = 20pF 50 °
Overload recovery time VIN  × gain > VS 130 ns
THD+N Total harmonic distortion + noise VS = 32V, VO = 3VRMS, G = 1, f = 1kHz, RL = 10kΩ 0.00022 %
113 dB
OUTPUT
  Voltage output swing from rail Positive and negative rail headroom VS = 32V, RL = no load   20 mV
VS = 32V, RL = 10kΩ   58 68
VS = 32V, RL = 2kΩ   117 137
VS = 5V, RL = no load 30
VS = 5V, RL = 10kΩ 45 52
VS = 5V, RL = 2kΩ 25 60
VS = 2.7V, RL = no load   25
VS = 2.7V, RL = 10kΩ   42 48
VS = 2.7V, RL = 2kΩ   45 54
ISC Short-circuit current VS = 32V ±62 ±125 mA
VS = 5V(1) ±50 ±85
VS = 2.7V(1) ±30 ±60
CLOAD Capacitive load drive Unlimited; See Phase Margin vs Capacitive Load pF
ZO Open-loop output impedance IO = 0A See Open-Loop Output Impedance vs Frequency Ω
POWER SUPPLY
IQ Quiescent current per amplifier VCM = V-, IO = 0A 1.35 1.93 mA
TA = –40°C to 125°C 2.23 mA
(1) Specified by characterization only.