SBOS853B March   2017  – December 2024 OPT3001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements #GUID-D86987F5-A9B7-4506-9858-90867D8ED8B3/SBOS6814062
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Human Eye Matching
      2. 6.3.2 Automatic Full-Scale Range Setting
      3. 6.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 6.3.4 I2C Bus Overview
        1. 6.3.4.1 Serial Bus Address
        2. 6.3.4.2 Serial Interface
    4. 6.4 Device Functional Modes
      1. 6.4.1 Automatic Full-Scale Setting Mode
      2. 6.4.2 Interrupt Reporting Mechanism Modes
        1. 6.4.2.1 Latched Window-Style Comparison Mode
        2. 6.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 6.4.2.3 End-of-Conversion Mode
        4. 6.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 6.5 Programming
      1. 6.5.1 Writing and Reading
        1. 6.5.1.1 High-Speed I2C Mode
        2. 6.5.1.2 General-Call Reset Command
        3. 6.5.1.3 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 Internal Registers
      1. 7.1.1 Register Descriptions
        1. 7.1.1.1 Result Register (offset = 00h)
        2. 7.1.1.2 Configuration Register (offset = 01h) [reset = C810h]
        3. 7.1.1.3 Low-Limit Register (offset = 02h) [reset = C0000h]
        4. 7.1.1.4 High-Limit Register (offset = 03h) [reset = BFFFh]
        5. 7.1.1.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
        6. 7.1.1.6 Device ID Register (offset = 7Fh) [reset = 3001h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Interface
      2. 8.1.2 Optical Interface
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Optomechanical Design
        2. 8.2.2.2 Dark Window Selection and Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Soldering and Handling Recommendations
    2. 11.2 DNP (S-PDSO-N6) Mechanical Drawings
    3. 11.3 DTS (SOT-5X3) Mechanical Drawings

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.1.3 SMBus Alert Response

The SMBus alert response provides a quick identification for which device issued the interrupt. Without this alert response capability, the processor does not know which device pulled the interrupt line when there are multiple target devices connected.

The OPT3001-Q1 device is designed to respond to the SMBus alert response address, when in the latched window-style comparison mode (configuration register, latch field = 1). The OPT3001-Q1 device does not respond to the SMBus alert response when in transparent mode (configuration register, latch field = 0).

The response behavior of the OPT3001-Q1 device to the SMBus alert response is shown in Figure 6-4. When the interrupt line to the processor is pulled to active, the controller can broadcast the alert response target address (0001 1001b). Following this alert response, any target devices that generated an alert can identify themselves by acknowledging the alert response and sending the respective I2C address on the bus. The alert response can activate several different target devices simultaneously. If more than one target attempts to respond, bus arbitration rules apply. The device with the lowest address wins the arbitration. If the OPT3001-Q1 device loses the arbitration, the device does not acknowledge the I2C transaction and the INT pin remains in an active state, prompting the I2C controller processor to issue a subsequent SMBus alert response. When the OPT3001-Q1 device wins the arbitration, the device acknowledges the transaction and sets the INT pin to inactive. The controller can issue that same command again, as many times as necessary to clear the INT pin. See the Section 6.4.2 section for additional details of how the flags and INT pin are controlled. The controller can obtain information about the source of the OPT3001-Q1 interrupt from the address broadcast in the above process. The flag high field (configuration register, bit 6) is sent as the final LSB of the address to provide the controller additional information about the cause of the OPT3001-Q1 interrupt. If the controller requires additional information, the result register or the configuration register can be queried. The flag high and flag low fields are not cleared upon an SMBus alert response.

OPT3001-Q1 Timing Diagram for SMBus Alert Response
A. FH is the flag high field (FH) in the configuration register (see Table 7-5).
B. A1 and A0 are determined by the ADDR pin; see Table 6-1.
Figure 6-4 Timing Diagram for SMBus Alert Response