SBOS929A December   2018  – December 2021 OPT3004

PRODMIX  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Description (continued)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Human Eye Matching
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Interrupt Operation, INT Pin, and Interrupt Reporting Mechanisms
      4. 8.3.4 I2C Bus Overview
        1. 8.3.4.1 Serial Bus Address
        2. 8.3.4.2 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Automatic Full-Scale Setting Mode
      2. 8.4.2 Interrupt Reporting Mechanism Modes
        1. 8.4.2.1 Latched Window-Style Comparison Mode
        2. 8.4.2.2 Transparent Hysteresis-Style Comparison Mode
        3. 8.4.2.3 End-of-Conversion Mode
        4. 8.4.2.4 End-of-Conversion and Transparent Hysteresis-Style Comparison Mode
    5. 8.5 Programming
      1. 8.5.1 Writing and Reading
        1. 8.5.1.1 High-Speed I2C Mode
        2. 8.5.1.2 General-Call Reset Command
        3. 8.5.1.3 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Internal Registers
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1 Result Register (offset = 00h)
        2. 8.6.2.2 Configuration Register (offset = 01h) [reset = C810h]
        3. 8.6.2.3 Low-Limit Register (offset = 02h) [reset = C0000h]
        4. 8.6.2.4 High-Limit Register (offset = 03h) [reset = BFFFh]
        5. 8.6.2.5 Manufacturer ID Register (offset = 7Eh) [reset = 5449h]
        6. 8.6.2.6 Device ID Register (offset = 7Fh) [reset = 3001h]
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Electrical Interface
      2. 9.1.2 Optical Interface
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Optomechanical Design
        2. 9.2.2.2 Dark Window Selection and Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  11. 10Power-Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Soldering and Handling Recommendations
    4. 11.4 DNP (S-PDSO-N6) Mechanical Drawings
    5. 11.5 DTS (SOT-5X3) Mechanical Drawings
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Timing Requirements

see note (1)
MINNOMMAXUNIT
I2C FAST MODE
fSCLSCL operating frequency0.010.4MHz
tBUFBus free time between stop and start1300ns
tHDSTAHold time after repeated start600ns
tSUSTASetup time for repeated start600ns
tSUSTOSetup time for stop600ns
tHDDATData hold time20900ns
tSUDATData setup time100ns
tLOWSCL clock low period1300ns
tHIGHSCL clock high period600ns
tRC and tFCClock rise and fall time300ns
tRD and tFDData rise and fall time300ns
tTIMEOBus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset.28ms
I2C HIGH-SPEED MODE
fSCLSCL operating frequency0.012.6MHz
tBUFBus free time between stop and start160ns
tHDSTAHold time after repeated start160ns
tSUSTASetup time for repeated start160ns
tSUSTOSetup time for stop160ns
tHDDATData hold time20140ns
tSUDATData setup time20ns
tLOWSCL clock low period240ns
tHIGHSCL clock high period60ns
tRC and tFCClock rise and fall time40ns
tRD and tFDData rise and fall time80ns
tTIMEOBus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset.28ms
All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of final settled value.
OPT3004 I2C Detailed Timing DiagramFigure 7-1 I2C Detailed Timing Diagram