SBOS929A December 2018 – December 2021 OPT3004
PRODMIX
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
I2C FAST MODE | |||||
fSCL | SCL operating frequency | 0.01 | 0.4 | MHz | |
tBUF | Bus free time between stop and start | 1300 | ns | ||
tHDSTA | Hold time after repeated start | 600 | ns | ||
tSUSTA | Setup time for repeated start | 600 | ns | ||
tSUSTO | Setup time for stop | 600 | ns | ||
tHDDAT | Data hold time | 20 | 900 | ns | |
tSUDAT | Data setup time | 100 | ns | ||
tLOW | SCL clock low period | 1300 | ns | ||
tHIGH | SCL clock high period | 600 | ns | ||
tRC and tFC | Clock rise and fall time | 300 | ns | ||
tRD and tFD | Data rise and fall time | 300 | ns | ||
tTIMEO | Bus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset. | 28 | ms | ||
I2C HIGH-SPEED MODE | |||||
fSCL | SCL operating frequency | 0.01 | 2.6 | MHz | |
tBUF | Bus free time between stop and start | 160 | ns | ||
tHDSTA | Hold time after repeated start | 160 | ns | ||
tSUSTA | Setup time for repeated start | 160 | ns | ||
tSUSTO | Setup time for stop | 160 | ns | ||
tHDDAT | Data hold time | 20 | 140 | ns | |
tSUDAT | Data setup time | 20 | ns | ||
tLOW | SCL clock low period | 240 | ns | ||
tHIGH | SCL clock high period | 60 | ns | ||
tRC and tFC | Clock rise and fall time | 40 | ns | ||
tRD and tFD | Data rise and fall time | 80 | ns | ||
tTIMEO | Bus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset. | 28 | ms |