SBOS864 August   2017 OPT3007

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Human Eye Matching
      2. 7.3.2 Automatic Full-Scale Range Setting
      3. 7.3.3 I2C Bus Overview
        1. 7.3.3.1 Serial Bus Address
        2. 7.3.3.2 Serial Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 Automatic Full-Scale Setting Mode
    5. 7.5 Programming
      1. 7.5.1 Writing and Reading
        1. 7.5.1.1 High-Speed I2C Mode
        2. 7.5.1.2 General-Call Reset Command
    6. 7.6 Register Maps
      1. 7.6.1 Internal Registers
        1. 7.6.1.1 Register Descriptions
          1. 7.6.1.1.1 Result Register (Offset = 00h)
          2. 7.6.1.1.2 Configuration Register (Offset = 01h) [Reset = C810h]
          3. 7.6.1.1.3 Low-Limit Register (Offset = 02h) [Reset = C0000h]
          4. 7.6.1.1.4 High-Limit Register (Offset = 03h) [Reset = BFFFh]
          5. 7.6.1.1.5 Manufacturer ID Register (Offset = 7Eh) [Reset = 5449h]
          6. 7.6.1.1.6 Device ID Register (Offset = 7Fh) [Reset = 3001h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Interface
      2. 8.1.2 Optical Interface
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Optomechanical Design
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Soldering and Handling Recommendations
      1. 10.2.1 Solder Paste
      2. 10.2.2 Package Placement
      3. 10.2.3 Reflow Profile
      4. 10.2.4 Special Flexible Printed-Circuit Board (FPCB) Recommendations
      5. 10.2.5 Rework Process
    3. 10.3 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The OPT3007 measures the ambient light that illuminates the device. This device measures light with a spectral response very closely matched to the human eye, and with very good infrared rejection.

Matching the sensor spectral response to that of the human eye response is vital because ambient light sensors are used to measure and help create ideal human lighting experiences. Strong rejection of infrared light, which a human does not see, is a crucial component of this matching. This matching makes the OPT3007 especially good for operation underneath windows that are visibly dark, but infrared transmissive.

The OPT3007 is fully self-contained to measure the ambient light and report the result in lux digitally over the I2C bus.

The OPT3007 can be configured into an automatic full-scale, range-setting mode that always selects the optimal full-scale range setting for the lighting conditions. This mode frees the user from having to program their software for potential iterative cycles of measurement and readjustment of the full-scale range until optimal for any given measurement. The device can be commanded to operate continuously or in single-shot measurement modes.

The device integrates its result over either 100 ms or 800 ms, so the effects of 50-Hz and 60-Hz noise sources from typical light bulbs are nominally reduced to a minimum.

The device starts up in a low-power shutdown state, such that the OPT3007 only consumes active-operation power after being programmed into an active state.

The OPT3007 optical filtering system is not excessively sensitive to non-ideal particles and micro-shadows on the optical surface. This reduced sensitivity is a result of the relatively minor device dependency on uniform-density optical illumination of the sensor area for infrared rejection. Proper optical surface cleanliness is always recommended for best results on all optical devices.

7.2 Functional Block Diagram

OPT3007 aij_BlockDiag_SBOS846.gif

7.3 Feature Description

7.3.1 Human Eye Matching

The OPT3007 spectral response closely matches that of the human eye. If the ambient light sensor measurement is used to help create a good human experience, or create optical conditions that are optimal for a human, the sensor must measure the same spectrum of light that a human sees.

The device also has excellent infrared light (IR) rejection. This IR rejection is especially important because many real-world lighting sources have significant infrared content that humans do not see. If the sensor measures infrared light that the human eye does not see, then a true human experience is not accurately represented.

Furthermore, if the ambient light sensor is hidden underneath a dark window (such that the end-product user cannot see the sensor) the infrared rejection of the OPT3007 becomes significantly more important because many dark windows attenuate visible light but transmit infrared light. This attenuation of visible light and lack of attenuation of IR light amplifies the ratio of the infrared light to visible light that illuminates the sensor. Results can still be well matched to the human eye under this condition because of the high infrared rejection of the OPT3007.

7.3.2 Automatic Full-Scale Range Setting

The OPT3007 has an automatic full-scale range setting feature that eliminates the need to predict and set the optimal range for the device. In this mode, the OPT3007 automatically selects the optimal full-scale range for the given lighting condition. The OPT3007 has a high degree of result matching between the full-scale range settings. This matching eliminates the problem of varying results or the need for range-specific, user-calibrated gain factors when different full-scale ranges are chosen. For further details, see the Automatic Full-Scale Setting Mode section.

7.3.3 I2C Bus Overview

The OPT3007 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another. The I2C interface is used throughout this document as the primary example with the SMBus protocol specified only when a difference between the two protocols is discussed.

The OPT3007 is connected to the bus with two pins: an SCL clock input pin and an SDA open-drain bidirectional data pin. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates start and stop conditions. To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a high logic level to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising edge, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge bit by pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition. When all data are transferred, the master generates a stop condition, indicated by pulling SDA from low to high while SCL is high. The OPT3007 includes a 28-ms timeout on the I2C interface to prevent locking up the bus. If the SCL line is held low for this duration of time, the bus state machine is reset.

7.3.3.1 Serial Bus Address

To communicate with the OPT3007, the master must first initiate an I2C start command. Then, the master must address slave devices via a slave address byte. The slave address byte consists of a seven bit address 1000101 and a direction bit that indicates whether the action is to be a read or write operation.

7.3.3.2 Serial Interface

The OPT3007 operates as a slave device on both the I2C bus and SMBus. Connections to the bus are made via the SCL clock input line and the SDA open-drain I/O line. The OPT3007 supports the transmission protocol for standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up to 2.6 MHz). All data bytes are transmitted most-significant bits first.

The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. See the Electrical Interface section for further details of the I2C bus noise immunity.

7.4 Device Functional Modes

7.4.1 Automatic Full-Scale Setting Mode

The OPT3007 has an automatic full-scale-range setting mode that eliminates the need for a user to predict and set the optimal range for the device. This mode is entered when the configuration register range number field (RN[3:0]) is set to 1100b.

The first measurement that the device takes in auto-range mode is a 10-ms range assessment measurement. The device then determines the appropriate full-scale range to take its first full measurement.

For subsequent measurements, the full-scale range is set by the result of the previous measurement. If a measurement is towards the low side of full-scale, the full-scale range is decreased by one or two settings for the next measurement. If a measurement is towards the upper side of full-scale, the full-scale range is increased by one setting for the next measurement.

If the measurement exceeds the full-scale range, resulting from a fast increasing optical transient event, the current measurement is aborted. This invalid measurement is not reported. If the scale is not at its maximum, the device increases the scale by one step and a new measurement is retaken with that scale. Therefore, during a fast increasing optical transient in this mode, a measurement can possibly take longer to complete and report than indicated by the configuration register conversion time field (CT).

7.5 Programming

The OPT3007 supports the transmission protocol for standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up to 2.6 MHz). Fast and standard modes are described as the default protocol, referred to as F/S. High-speed mode is described in the High-Speed I2C Mode section.

7.5.1 Writing and Reading

Accessing a specific register on the OPT3007 is accomplished by writing the appropriate register address during the I2C transaction sequence. Refer to Table 1 for a complete list of registers and their corresponding register addresses. The value for the register address (as shown in Figure 19) is the first byte transferred after the slave address byte with the R/W bit low.

OPT3007 aij_I2CPointerWr_v2.gif Figure 19. Setting the I2C Register Address

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address with the R/W bit low. The OPT3007 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register that data are to be written to. The next two bytes are written to the register addressed by the register address. The OPT3007 acknowledges receipt of each data byte. The master may terminate the data transfer by generating a start or stop condition.

When reading from the OPT3007, the last value stored in the register address by a write operation determines which register is read during a read operation. To change the register address for a read operation, a new partial I2C write transaction must be initiated. This partial write is accomplished by issuing a slave address byte with the R/W bit low, followed by the register address byte and a stop command. The master then generates a start condition and sends the slave address byte with the R/W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register address. This byte is followed by an acknowledge from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate the data transfer by generating a not-acknowledge after receiving any data byte, or by generating a start or stop condition. If repeated reads from the same register are desired, continually sending the register address bytes is not necessary; the OPT3007 retains the register address until that number is changed by the next write operation.

Figure 20 and Figure 21 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most significant byte first, followed by the least significant byte.

OPT3007 aij_I2CWrite_v2.gif Figure 20. I2C Write Example
OPT3007 aij_I2CRead_v2.gif
1. An ACK by the master can also be sent.
Figure 21. I2C Read Example

7.5.1.1 High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors or active pullup devices. The master generates a start condition followed by a valid serial byte containing the high-speed (HS) master code 0000 1XXXb. This transmission is made in either standard mode or fast mode (up to 400 kHz). The OPT3007 does not acknowledge the HS master code but does recognize the code and switches its internal filters to support a 2.6-MHz operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 2.6 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the bus in HS mode. A stop condition ends the HS mode and switches all internal filters of the OPT3007 to support the F/S mode.

7.5.1.2 General-Call Reset Command

The I2C general-call reset allows the host controller in one command to reset all devices on the bus that respond to the general-call reset command. The general call is initiated by writing to the I2C address 0 (0000 0000b). The reset command is initiated when the subsequent second address byte is 06h (0000 0110b). With this transaction, the device issues an acknowledge bit and sets all of its registers to the power-on-reset default condition.

7.6 Register Maps

7.6.1 Internal Registers

The device is operated over the I2C bus with registers that contain configuration, status, and result information. All registers are 16 bits long.

There are four main registers: result, configuration, low-limit, and high-limit. There are also two ID registers: manufacturer ID and device ID. Table 1 lists these registers.

Table 1. Register Map

REGISTER ADDRESS (HEX)(1) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Result 00h E3 E2 E1 E0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Configuration 01h RN3 RN2 RN1 RN0 CT M1 M0 OVF CRF FH FL L POL ME FC1 FC0
Low Limit 02h LE3 LE2 LE1 LE0 TL11 TL10 TL9 TL8 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0
High Limit 03h HE3 HE2 HE1 HE0 TH11 TH10 TH9 TH8 TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0
Manufacturer ID 7Eh ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Device ID 7Fh DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8 DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0
(1) Register offset and register address are used interchangeably.

7.6.1.1 Register Descriptions

NOTE

Register offset and register address are used interchangeably.

7.6.1.1.1 Result Register (Offset = 00h)

This register contains the result of the most recent light to digital conversion. This 16-bit register has two fields: a 4-bit exponent and a 12-bit mantissa.

Figure 22. Result Register (Read-Only)
15 14 13 12 11 10 9 8
E3 E2 E1 E0 R11 R10 R9 R8
R R R R R R R R
7 6 5 4 3 2 1 0
R7 R6 R5 R4 R3 R2 R1 R0
R R R R R R R R
LEGEND: R = Read only

Table 2. Result Register Field Descriptions

Bit Field Type Reset Description
15:12 E[3:0] R 0h Exponent.
These bits are the exponent bits. Table 3 provides further details.
11:0 R[11:0] R 000h Fractional result.
These bits are the result in straight binary coding (zero to full-scale).

Table 3. Full-Scale Range and LSB Size as a Function of Exponent Level

E3 E2 E1 E0 FULL-SCALE RANGE (lux) LSB SIZE (lux per LSB)
0 0 0 0 40.95 0.01
0 0 0 1 81.90 0.02
0 0 1 0 163.80 0.04
0 0 1 1 327.60 0.08
0 1 0 0 655.20 0.16
0 1 0 1 1310.40 0.32
0 1 1 0 2620.80 0.64
0 1 1 1 5241.60 1.28
1 0 0 0 10483.20 2.56
1 0 0 1 20966.40 5.12
1 0 1 0 41932.80 10.24
1 0 1 1 83865.60 20.48

The formula to translate this register into lux is given in Equation 1:

Equation 1. lux = LSB_Size × R[11:0]

where

  • LSB_Size = 0.01 × 2E[3:0]

LSB_Size can also be taken from Table 3. The complete lux equation is shown in Equation 2:

Equation 2. lux = 0.01 × (2E[3:0]) × R[11:0]

A series of result register output examples with the corresponding LSB weight and resulting lux are given in Table 4. Note that many combinations of exponents (E[3:0]) and fractional results (R[11:0]) can map onto the same lux result, as shown in the examples of Table 4.

Table 4. Examples of Decoding the Result Register into lux

RESULT REGISTER
(BITS 15:0, BINARY)		 EXPONENT
(E[3:0], HEX)		 FRACTIONAL RESULT
(R[11:0], HEX)		 LSB WEIGHT
(LUX, DECIMAL)		 RESULTING LUX (DECIMAL)
0000 0000 0000 0001b 00h 001h 0.01 0.01
0000 1111 1111 1111b 00h FFFh 0.01 40.95
0011 0100 0101 0110b 03h 456h 0.08 88.80
0111 1000 1001 1010b 07h 89Ah 1.28 2818.56
1000 1000 0000 0000b 08h 800h 2.56 5242.88
1001 0100 0000 0000b 09h 400h 5.12 5242.88
1010 0010 0000 0000b 0Ah 200h 10.24 5242.88
1011 0001 0000 0000b 0Bh 100h 20.48 5242.88
1011 0000 0000 0001b 0Bh 001h 20.48 20.48
1011 1111 1111 1111b 0Bh FFFh 20.48 83865.60

Note that the exponent field can be disabled (set to zero) by enabling the exponent mask (configuration register, ME field = 1) and manually programming the full-scale range (configuration register, RN[3:0] < 1100b (0Ch)), allowing for simpler operation in a manually-programmed, full-scale mode. Calculating lux from the result register contents only requires multiplying the result register by the LSB weight (in lux) associated with the specific programmed full-scale range (see Table 3). See the Low-Limit Register for details.

See the configuration register conversion time field (CT, bit 11) description for more information on lux resolution as a function of conversion time.

7.6.1.1.2 Configuration Register (Offset = 01h) [Reset = C810h]

This register controls the major operational modes of the device. This register has 11 fields, which are documented below. If a measurement conversion is in progress when the configuration register is written, the active measurement conversion immediately aborts. If the new configuration register directs a new conversion, that conversion is subsequently started.

Figure 23. Configuration Register
15 14 13 12 11 10 9 8
RN3 RN2 RN1 RN0 CT M1 M0 OVF
R/W R/W R/W R/W R/W R/W R/W R
7 6 5 4 3 2 1 0
CRF FH FL L POL ME FC1 FC0
R R R R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

Table 5. Configuration Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15:12 RN[3:0] R/W 1100b Range number field (read or write).
The range number field selects the full-scale lux range of the device. The format of this field is the same as the result register exponent field (E[3:0]); see Table 3. When RN[3:0] is set to 1100b (0Ch), the device operates in automatic full-scale setting mode, as described in the Automatic Full-Scale Setting Mode section. In this mode, the automatically chosen range is reported in the result exponent (register 00h, E[3:0]).
The device powers up as 1100 in automatic full-scale setting mode. Codes 1101b, 1110b, and 1111b (0Dh, 0Eh, and 0Fh) are reserved for future use.
11 CT R/W 1b Conversion time field (read or write).
The conversion time field determines the length of the light to digital conversion process. The choices are 100 ms and 800 ms. A longer integration time allows for a lower noise measurement.
The conversion time also relates to the effective resolution of the data conversion process. The 800-ms conversion time allows for the fully specified lux resolution. The 100-ms conversion time with full-scale ranges above 0101b for E[3:0] in the result and configuration registers also allows for the fully specified lux resolution. The 100-ms conversion time with full-scale ranges below and including 0101b for E[3:0] can reduce the effective result resolution by up to three bits, as a function of the selected full-scale range. Range 0101b reduces by one bit. Ranges 0100b, 0011b, 0010b, and 0001b reduces by two bits. Range 0000b reduces by three bits. The result register format and associated LSB weight does not change as a function of the conversion time.
0 = 100 ms
1 = 800 ms
10:9 M[1:0] R/W 00b Mode of conversion operation field (read or write).
The mode of conversion operation field controls whether the device is operating in continuous conversion, single-shot, or low-power shutdown mode. The default is 00b (shutdown mode), such that upon power-up, the device only consumes operational level power after appropriately programming the device.
When single-shot mode is selected by writing 01b to this field, the field continues to read 01b while the device is actively converting. When the single-shot conversion is complete, the mode of conversion operation field is automatically set to 00b and the device is shut down.

00 = Shutdown (default)
01 = Single-shot
10, 11 = Continuous conversions
8 OVF R 0b Overflow flag field (read-only).
The overflow flag field indicates when an overflow condition occurs in the data conversion process, typically because the light illuminating the device exceeds the programmed full-scale range of the device. Under this condition OVF is set to 1, otherwise OVF remains at 0. The field is reevaluated on every measurement.
If the full-scale range is manually set (RN[3:0] field < 1100b), the overflow flag field can be set while the result register reports a value less than full-scale. This result occurs if the input light has a temporary high spike level that temporarily overloads the integrating ADC converter circuitry but returns to a level within range before the conversion is complete. Thus, the overflow flag reports a possible error in the conversion process. This behavior is common to integrating-style converters.
If the full-scale range is automatically set (RN[3:0] field = 1100b), the only condition that sets the overflow flag field is if the input light is beyond the full-scale level of the entire device. When there is an overflow condition and the full-scale range is not at maximum, the OPT3007 aborts its current conversion, sets the full-scale range to a higher level, and starts a new conversion. The flag is set at the end of the process to indicate a scale increase and that a new measurement is being taken. This process repeats until there is either no overflow condition or until the full-scale range is set to its maximum range.
7 CRF R 0b Conversion ready field (read-only).
The conversion ready field indicates when a conversion completes. The field is set to 1 at the end of a conversion and is cleared (set to 0) when the configuration register is subsequently read or written with any value except one containing the shutdown mode (mode of operation field, M[1:0] = 00b). Writing a shutdown mode does not affect the state of this field.
6 FH R 0b Flag high field (read-only).
The flag high field (FH) identifies that the result of a conversion is larger than a specified level of interest. FH is set to 1 when the result is larger than the level in the high-limit register (register address 03h) for a consecutive number of measurements defined by the fault count field (FC[1:0]).
5 FL R 0b Flag low field (read-only).
The flag low field (FL) identifies that the result of a conversion is smaller than a specified level of interest. FL is set to 1 when the result is smaller than the level in the low-limit register (register address 02h) for a consecutive number of measurements defined by the fault count field (FC[1:0]).
4 L R 1b Unused
2 ME R/W 0b Mask exponent field (read or write).
The mask exponent field forces the result register exponent field (register 00h, bits E[3:0]) to 0000b when the full-scale range is manually set, which can simplify the processing of the result register when the full-scale range is manually programmed. This behavior occurs when the mask exponent field is set to 1 and the range number field (RN[3:0]) is set to less than 1100b. Note that the masking is only performed to the result register.
1:0 FC[1:0] R/W 00b Fault count field (read or write).
The fault count field instructs the device as to how many consecutive fault events are required to trigger the interrupt reporting mechanisms: the flag high field (FH) and the flag low field (FL). The fault events are described in the flag high field (FH), and flag low field (FL) descriptions.
00 = One fault count (default)
01 = Two fault counts
10 = Four fault counts
11 = Eight fault counts

7.6.1.1.3 Low-Limit Register (Offset = 02h) [Reset = C0000h]

This register sets the lower comparison limit for the interrupt reporting mechanisms: the flag high field (FH) and the flag low field (FL).

Figure 24. Low-Limit Register
15 14 13 12 11 10 9 8
LE3 LE2 LE1 LE0 TL11 TL10 TL9 TL8
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 6. Low-Limit Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15:12 LE[3:0] R/W 0h Exponent.
These bits are the exponent bits. Table 7 provides further details.
11:0 TL[11:0] R/W 000h Result.
These bits are the result in straight binary coding (zero to full-scale).

The format of this register is nearly identical to the format of the result register described in the Result Register. The low-limit register exponent (LE[3:0]) is similar to the result register exponent (E[3:0]). The low-limit register result (TL[11:0]) is similar to result register result (R[11:0]).

The equation to translate this register into the lux threshold is given in Equation 3, which is similar to the equation for the result register, Equation 2.

Equation 3. lux = 0.01 × (2LE[3:0]) × TL[11:0]

Table 7 gives the full-scale range and LSB size as it applies to the low-limit register. The detailed discussion and examples given in for the Result Register apply to the low-limit register as well.

Table 7. Full-Scale Range and LSB Size as a Function of Exponent Level

LE3 LE2 LE1 LE0 FULL-SCALE RANGE (lux) LSB SIZE (lux per LSB)
0 0 0 0 40.95 0.01
0 0 0 1 81.90 0.02
0 0 1 0 163.80 0.04
0 0 1 1 327.60 0.08
0 1 0 0 655.20 0.16
0 1 0 1 1310.40 0.32
0 1 1 0 2620.80 0.64
0 1 1 1 5241.60 1.28
1 0 0 0 10483.20 2.56
1 0 0 1 20966.40 5.12
1 0 1 0 41932.80 10.24
1 0 1 1 83865.60 20.48

NOTE

The result and limit registers are all converted into lux values internally for comparison. These registers can have different exponent fields. However, when using a manually-set full-scale range (configuration register, RN < 0Ch, with mask enable (ME) active), programming the manually-set full-scale range into the LE[3:0] and HE[3:0] fields can simplify the choice of programming the register. This simplification results in the user only having to think about the fractional result and not the exponent part of the result.

7.6.1.1.4 High-Limit Register (Offset = 03h) [Reset = BFFFh]

The high-limit register sets the upper comparison limit for the interrupt reporting mechanisms: the flag high field (FH) and the flag low field (FL). The format of this register is almost identical to the format of the low-limit register (described in the Low-Limit Register) and the result register (described in the Result Register). To explain the similarity in more detail, the high-limit register exponent (HE[3:0]) is similar to the low-limit register exponent (LE[3:0]) and the result register exponent (E[3:0]). The high-limit register result (TH[11:0]) is similar to the low-limit result (TH[11:0]) and the result register result (R[11:0]). Note that the comparison of the high-limit register with the result register is unaffected by the ME bit.

When using a manually-set, full-scale range with the mask enable (ME) active, programming the manually-set, full-scale range into the HE[3:0] bits can simplify the choice of values required to program into this register. The formula to translate this register into lux is similar to Equation 3. The full-scale values are similar to Table 3.

Figure 25. High-Limit Register
15 14 13 12 11 10 9 8
HE3 HE2 HE1 HE0 TH11 TH10 TH9 TH8
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 8. High-Limit Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15:12 HE[3:0] R/W Bh Exponent.
These bits are the exponent bits.
11:0 TH[11:0] R/W FFFh Result.
These bits are the result in straight binary coding (zero to full-scale).

7.6.1.1.5 Manufacturer ID Register (Offset = 7Eh) [Reset = 5449h]

This register is intended to help uniquely identify the device.

Figure 26. Manufacturer ID Register
15 14 13 12 11 10 9 8
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
R R R R R R R R
7 6 5 4 3 2 1 0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
R R R R R R R R
LEGEND: R = Read only

Table 9. Manufacturer ID Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15:0 ID[15:0] R 5449h Manufacturer ID.
The manufacturer ID reads 5449h. In ASCII code, this register reads TI.

7.6.1.1.6 Device ID Register (Offset = 7Fh) [Reset = 3001h]

This register is also intended to help uniquely identify the device.

Figure 27. Device ID Register
15 14 13 12 11 10 9 8
DID15 DID14 DID13 DID12 DID11 DID10 DID9 DID8
R R R R R R R R
7 6 5 4 3 2 1 0
DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0
R R R R R R R R
LEGEND: R = Read only

Table 10. Device ID Register Field Descriptions

BIT FIELD TYPE RESET DESCRIPTION
15:0 DID[15:0] R 3001h Device ID.
The device ID reads 3001h.