SBOS864 August 2017 OPT3007
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | VDD to GND | –0.5 | 6 | V |
SDA and SCL to GND | –0.5 | 6 | V | |
Current into any pin | 10 | mA | ||
Temperature | Junction | 150 | °C | |
Storage, Tstg | –65 | 150(2) | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Operating temperature | –40 | 85 | °C | ||
Operating power-supply voltage | 1.6 | 3.6 | V |
THERMAL METRIC(1) | OPT3007 | UNIT | |
---|---|---|---|
YMF (PicoStar) | |||
6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 122.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 1.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 34.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 35.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OPTICAL | |||||||
Peak irradiance spectral responsivity | 550 | nm | |||||
Resolution (LSB) | Lowest full-scale range, RN[3:0] = 0000b(2) | 0.01 | lux | ||||
Full-scale illuminance | 83865.6 | lux | |||||
Measurement output result | 0.64 lux per ADC code, 2620.80 lux full-scale (RN[3:0] = 0110)(2), 2000 lux input(3) | 2500 | 3125 | 3750 | ADC codes | ||
1600 | 2000 | 2400 | lux | ||||
Relative accuracy between gain ranges(1) | 0.2% | ||||||
Infrared response (850 nm)(3) | 0.2% | ||||||
Light source variation (incandescent, halogen, fluorescent) |
Bare device, no cover glass | 4% | |||||
Linearity | Input illuminance > 40 lux | 2% | |||||
Input illuminance < 40 lux | 5% | ||||||
Measurement drift across temperature | Input illuminance = 2000 lux | 0.01 | %/°C | ||||
Dark condition, ADC output | 0.01 lux per ADC code | 0 | 3 | ADC codes | |||
0 | 0.03 | lux | |||||
Half-power angle | 50% of full-power reading | 44 | degrees | ||||
PSRR | Power-supply rejection ratio | VDD at 3.6 V and 1.6 V | 0.1 | %/V(4) | |||
POWER SUPPLY | |||||||
VDD | Operating range | 1.6 | 3.6 | V | |||
VI²C | Operating range of I2C pull-up resistor | I2C pullup resistor, VDD ≤ VI²C | 1.6 | 5.5 | V | ||
IQ | Quiescent current | Dark | Active, VDD = 3.6 V | 1.8 | 2.5 | µA | |
Shutdown (M[1:0] = 00)(2), VDD = 3.6 V | 0.3 | 0.47 | µA | ||||
Full-scale lux | Active, VDD = 3.6 V | 3.7 | µA | ||||
Shutdown, (M[1:0] = 00)(2) |
0.4 | µA | |||||
POR | Power-on-reset threshold | TA = 25°C | 0.8 | V | |||
DIGITAL | |||||||
I/O pin capacitance | 3 | pF | |||||
Total integration time(5) | (CT = 1)(2), 800-ms mode, fixed lux range | 720 | 800 | 880 | ms | ||
(CT = 0)(2), 100-ms mode, fixed lux range | 90 | 100 | 110 | ms | |||
VIL | Low-level input voltage (SDA and SCL) |
0 | 0.3 × VDD | V | |||
VIH | High-level input voltage (SDA and SCL) |
0.7 × VDD | 5.5 | V | |||
IIL | Low-level input current (SDA and SCL) |
0.01 | 0.25(6) | µA | |||
VOL | Low-level output voltage (SDA) |
IOL= 3 mA | 0.32 | V | |||
IZH | Output logic high, high-Z leakage current (SDA) | Pin at VDD | 0.01 | 0.25(6) | µA | ||
TEMPERATURE | |||||||
Specified temperature range | –40 | 85 | °C |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
I2C FAST MODE | |||||
fSCL | SCL operating frequency | 0.01 | 0.4 | MHz | |
tBUF | Bus free time between stop and start | 1300 | ns | ||
tHDSTA | Hold time after repeated start | 600 | ns | ||
tSUSTA | Setup time for repeated start | 600 | ns | ||
tSUSTO | Setup time for stop | 600 | ns | ||
tHDDAT | Data hold time | 20 | 900 | ns | |
tSUDAT | Data setup time | 100 | ns | ||
tLOW | SCL clock low period | 1300 | ns | ||
tHIGH | SCL clock high period | 600 | ns | ||
tRC and tFC | Clock rise and fall time | 300 | ns | ||
tRD and tFD | Data rise and fall time | 300 | ns | ||
tTIMEO | Bus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset. | 28 | ms | ||
I2C HIGH-SPEED MODE | |||||
fSCL | SCL operating frequency | 0.01 | 2.6 | MHz | |
tBUF | Bus free time between stop and start | 160 | ns | ||
tHDSTA | Hold time after repeated start | 160 | ns | ||
tSUSTA | Setup time for repeated start | 160 | ns | ||
tSUSTO | Setup time for stop | 160 | ns | ||
tHDDAT | Data hold time | 20 | 140 | ns | |
tSUDAT | Data setup time | 20 | ns | ||
tLOW | SCL clock low period | 240 | ns | ||
tHIGH | SCL clock high period | 60 | ns | ||
tRC and tFC | Clock rise and fall time | 40 | ns | ||
tRD and tFD | Data rise and fall time | 80 | ns | ||
tTIMEO | Bus timeout period. If the SCL line is held low for this duration of time, the bus state machine is reset. | 28 | ms |
Input illuminance = 960 lux, normalized to response of 2560 lux full-scale |
M[1:0] = 10b |
M[1:0] = 10b |
Input illuminance = 80 lux, SCL = SDA, continuously toggled at I2C frequency Note: A typical application runs at a lower duty cycle and thus consumes a lower current. |
Input illuminance = 30 lux, normalized to response of 40.95 lux full-scale |
Average of 30 devices | ||
M[1:0] = 00b |
M[1:0] = 00b, input illuminance = 0 lux |