SBAS883A February 2018 – June 2018 OPT3101
PRODUCTION DATA.
Monoshot mode is a low-power mode. In this mode, the device is in a deep sleep state and waits for an external trigger. The sample can be initiated by an RST_MS pin (active-low) trigger or the register trigger (MONOSHOT_BIT). On trigger, the device comes out of power down, waits for the programmed delay (POWERUP_DELAY) to start a frame, captures the specified number of samples (MONOSHOT_NUMFRAME), then goes into a deep sleep state to save power. A new interrupt is serviced only after completing the current frame capture. Any interrupt during the capture of a frame is discarded. Figure 15 shows the timing diagram of the monoshot mode with the RST_MS pin trigger. From the trigger, the frame start can be delayed by setting the POWERUP_DELAY register. The delay between the trigger and the sample start (FR_VD signal in Figure 15) is (64 × POWERUP_DELAY + 2) × tCLK. A minimum delay of 0.4 ms is required for the device to come out of the deep sleep state. A maximum of 26.2 ms delay can be programmed. This mode can also be used for synchronized capture from an external host.
The RST_MS pin is a dual-purpose pin used for reset and monoshot triggering. For reset, give a pulse duration that is > 30 µs. For monoshot trigger, give a pulse duration that is < 1 µs and > 100 ns.
For register-triggered monoshot mode, the host writes 1 to the interrupt register (MONOSHOT_BIT) to initiate sample capture. Once the data ready of the Nth sample is available, the device automatically clears the interrupt register bit and goes into deep sleep state.
PARAMETER | ADDRESS | DESCRIPTION |
---|---|---|
MONOSHOT_MODE | 27h[1:0] | 0: Continuous mode | 3: Monoshot mode | Other values: Not valid |
MONOSHOT_NUMFRAME | 27h[7:2] | Number of frames to be captured for every trigger. |
POWERUP_DELAY | 26h[23:10] | Register to program the delay from the external trigger to start of frame (FRAME_VD).
Delay = (64 × POWERUP_DELAY + 2) × tCLK, tCLK = 25 ns. |
MONOSHOT_BIT | 0h[23] | Monoshot trigger register.
Write 1 to start sample capture. The bit is auto cleared after capture completion. |