SBOSA93C May 2023 – June 2024 OPT4001-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
To communicate with the OPT4001-Q1, the controller must first initiate an I2C start command. Then, the controller must address target devices through a target address byte. The target address byte consists of a seven bit address and a direction bit that indicates whether the action is to be a read or write operation.
For the USON variant, four I2C addresses are possible by connecting the ADDR pin to one of four pins: GND, VDD, SDA, or SCL. Table 6-7 summarizes the possible addresses with the corresponding ADDR pin configuration. The state of the ADDR pin is sampled on every bus communication and must be driven or connected to the desired level before any activity on the interface occurs.
ADDR PIN CONNECTION | DEVICE I2C ADDRESS |
---|---|
GND | 1000100 |
VDD | 1000101 |
SDA | 1000110 |
SCL | 1000111 |
In the case of the PicoStarâ„¢ variant there is no target address selection capability and the device address is hard coded to 1000101b (0x45).