SBOSA93C May 2023 – June 2024 OPT4001-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The OPT4001-Q1 operates as a target device on both the I2C bus and SMBus. Connections to the bus are made through the SCL clock input line and the SDA open-drain I/O line. The device supports the transmission protocol for standard mode (up to 100 kHz), fast mode (up to 400 kHz), and high-speed mode (up to 2.6 MHz). All data bytes are transmitted most significant bits first.
The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. See the Electrical Interface section for further details of the I2C bus noise immunity.