SBOSA93C May 2023 – June 2024 OPT4001-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The OPT4001-Q1 supports I2C burst read mode, which helps minimize the number of transactions on the bus for efficient data transfer from the device to the controller.
Before considering the burst mode, a regular I2C read transaction involves an I2C write operation to the device read pointer, followed by the actual I2C read operation. If regular I2C read transactions are performed when reading from the output registers and FIFO registers, which are in continuous locations, then the register pointer is written every two bytes and this process takes up several clock cycles. With the burst mode enabled, the read pointer address is auto incremented after every register read (two bytes), eliminating the need to write operations to set the pointer for subsequent register reads.
Set the I2C_BURST register to enable burst mode. When a stop command is issued, the pointer resets to the original register address before the auto-increments. Figure 6-8 shows a diagram of the I2C write, single read, and burst mode read operation.