SBOSA93C May   2023  – June 2024 OPT4001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Spectral Matching to Human Eye
      2. 6.3.2 Automatic Full-Scale Range Setting
      3. 6.3.3 Error Correction Code (ECC) Features
        1. 6.3.3.1 Output Sample Counter
        2. 6.3.3.2 Output CRC
      4. 6.3.4 Output Register FIFO
      5. 6.3.5 Threshold Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
      2. 6.4.2 Interrupt Modes of Operation
      3. 6.4.3 Light Range Selection
      4. 6.4.4 Selecting Conversion Time
      5. 6.4.5 Light Measurement in Lux
      6. 6.4.6 Threshold Detection Calculations
      7. 6.4.7 Light Resolution
    5. 6.5 Programming
      1. 6.5.1 I2C Bus Overview
        1. 6.5.1.1 Serial Bus Address
        2. 6.5.1.2 Serial Interface
      2. 6.5.2 Writing and Reading
        1. 6.5.2.1 High-Speed I2C Mode
        2. 6.5.2.2 Burst Read Mode
        3. 6.5.2.3 General-Call Reset Command
        4. 6.5.2.4 SMBus Alert Response (USON Variant)
  8. 7 Register Maps
    1. 7.1 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Electrical Interface
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Optical Interface
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Optomechanical Design (PicoStar Variant)
          2. 8.2.1.2.2 Optomechanical Design (USON Variant)
        3. 8.2.1.3 Application Curves (PicoStar Variant)
        4. 8.2.1.4 Application Curves (USON Variant)
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Soldering and Handling Recommendations (PicoStar Variant)
          1. 8.5.1.1.1 Solder Paste
          2. 8.5.1.1.2 Package Placement
          3. 8.5.1.1.3 Reflow Profile
          4. 8.5.1.1.4 Special Flexible Printed-Circuit Board (FPCB) Recommendations
          5. 8.5.1.1.5 Rework Process
        2. 8.5.1.2 Soldering and Handling Recommendations (USON Variant)
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DNP|6
  • YMN|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Register Descriptions

7.1.1 Register 0h (offset = 0h) [reset = 0h]

Figure 7-2 Register 0h
15141312111098
EXPONENTRESULT_MSB
R-0hR-0h
76543210
RESULT_MSB
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-3 Register 00 Field Descriptions
BitFieldTypeResetDescription
15-12EXPONENTR0hEXPONENT output. Determines the full-scale range of the light measurement. Used as a scaling factor for lux calculation
11-0RESULT_MSBR0hResult register MSB (Most significant bits). Used to calculate the MANTISSA representing light level within a given EXPONENT or full-scale range

7.1.2 Register 1h (offset = 1h) [reset = 0h]

Figure 7-4 Register 1h
15141312111098
RESULT_LSB
R-0h
76543210
COUNTERCRC
R-0hR-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-5 Register 01 Field Descriptions
BitFieldTypeResetDescription
15-8RESULT_LSBR0hResult register LSB (Least significant bits). Used to calculate MANTISSA representing light level within a given EXPONENT or full-scale range
7-4COUNTERR0hSample counter. Rolling counter which increments for every conversion
3-0CRCR0hCRC bits.
R[19:0]=MANTISSA=((RESULT_MSB<<8)+ RESULT_LSB
X[0]=XOR(E[3:0],R[19:0],C[3:0]) XOR of all bits
X[1]=XOR(C[1],C[3],R[1],R[3],R[5],R[7],R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])
X[2]=XOR(C[3],R[3],R[7],R[11],R[15],R[19],E[3])
X[3]=XOR(R[3],R[11],R[19])

7.1.3 Register 2h (offset = 2h) [reset = 0h]

Figure 7-6 Register 2h
15141312111098
EXPONENT_FIFO0RESULT_MSB_FIFO0
R-0hR-0h
76543210
RESULT_MSB_FIFO0
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-7 Register 02 Field Descriptions
BitFieldTypeResetDescription
15-12EXPONENT_FIFO0R0hEXPONENT register from FIFO 0
11-0RESULT_MSB_FIFO0R0hRESULT_MSB Register from FIFO 0

7.1.4 Register 3h (offset = 3h) [reset = 0h]

Figure 7-8 Register 3h
15141312111098
RESULT_LSB_FIFO0
R-0h
76543210
COUNTER_FIFO0CRC_FIFO0
R-0hR-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-9 Register 03 Field Descriptions
BitFieldTypeResetDescription
15-8RESULT_LSB_FIFO0R0hRESULT_LSB Register from FIFO 0
7-4COUNTER_FIFO0R0hCOUNTER Register from FIFO 0
3-0CRC_FIFO0R0hCRC Register from FIFO 0

7.1.5 Register 4h (offset = 4h) [reset = 0h]

Figure 7-10 Register 4h
15141312111098
EXPONENT_FIFO1RESULT_MSB_FIFO1
R-0hR-0h
76543210
RESULT_MSB_FIFO1
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-11 Register 04 Field Descriptions
BitFieldTypeResetDescription
15-12EXPONENT_FIFO1R0hEXPONENT register from FIFO 1
11-0RESULT_MSB_FIFO1R0hRESULT_MSB Register from FIFO 1

7.1.6 Register 5h (offset = 5h) [reset = 0h]

Figure 7-12 Register 5h
15141312111098
RESULT_LSB_FIFO1
R-0h
76543210
COUNTER_FIFO1CRC_FIFO1
R-0hR-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-13 Register 05 Field Descriptions
BitFieldTypeResetDescription
15-8RESULT_LSB_FIFO1R0hRESULT_LSB Register from FIFO 1
7-4COUNTER_FIFO1R0hCOUNTER Register from FIFO 1
3-0CRC_FIFO1R0hCRC Register from FIFO 1

7.1.7 Register 6h (offset = 6h) [reset = 0h]

Figure 7-14 Register 6h
15141312111098
EXPONENT_FIFO2RESULT_MSB_FIFO2
R-0hR-0h
76543210
RESULT_MSB_FIFO2
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-15 Register 06 Field Descriptions
BitFieldTypeResetDescription
15-12EXPONENT_FIFO2R0hEXPONENT register from FIFO 2
11-0RESULT_MSB_FIFO2R0hRESULT_MSB Register from FIFO 2

7.1.8 Register 7h (offset = 7h) [reset = 0h]

Figure 7-16 Register 7h
15141312111098
RESULT_LSB_FIFO2
R-0h
76543210
COUNTER_FIFO2CRC_FIFO2
R-0hR-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-17 Register 07 Field Descriptions
BitFieldTypeResetDescription
15-8RESULT_LSB_FIFO2R0hRESULT_LSB Register from FIFO 2
7-4COUNTER_FIFO2R0hCOUNTER Register from FIFO 2
3-0CRC_FIFO2R0hCRC Register from FIFO 2

7.1.9 Register 8h (offset = 8h) [reset = 0h]

Figure 7-18 Register 8h
15141312111098
THRESHOLD_L_EXPONENTTHRESHOLD_L_RESULT
R/W-0hR/W-0h
76543210
THRESHOLD_L_RESULT
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-19 Register 08 Field Descriptions
BitFieldTypeResetDescription
15-12THRESHOLD_L_EXPONENTR/W0hThreshold low register exponent
11-0THRESHOLD_L_RESULTR/W0hThreshold low register result

7.1.10 Register 9h (offset = 9h) [reset = BFFFh]

Figure 7-20 Register 9h
15141312111098
THRESHOLD_H_EXPONENTTHRESHOLD_H_RESULT
R/W-BhR/W-Fh
76543210
THRESHOLD_H_RESULT
R/W-FFh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-21 Register 09 Field Descriptions
BitFieldTypeResetDescription
15-12THRESHOLD_H_EXPONENTR/WBhThreshold high register exponent
11-0THRESHOLD_H_RESULTR/WFFFhThreshold high register result

7.1.11 Register Ah (offset = Ah) [reset = 3208h]

Figure 7-22 Register Ah
15141312111098
QWAKE0RANGECONVERSION_TIME
R/W-0hR/W-0hR/W-ChR/W-2h
76543210
CONVERSION_TIMEOPERATING_MODELATCHINT_POLFAULT_COUNT
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-23 Register 0A Field Descriptions
BitFieldTypeResetDescription
15-15QWAKER/W0hQuick wake-up from standby in one-shot mode by not powering down all circuits. Applicable only in one-shot mode and helps get out of standby mode faster with penalty in power consumption compared to full standby mode.
14-140R/W0hMust read or write 0
13-10RANGER/WChControls the full-scale light level range of the device. The format of this register is same as the EXPONENT register for all values from 0 to 8.
PicoStar™ variant:
0 : 328lux
1 : 655lux
2 : 1.3klux
3 : 2.6klux
4 : 5.2klux
5 : 10.5klux
6 : 21klux
7 : 42klux
8 : 83klux
12 : Auto-Range
USON variant:
0 : 419lux
1 : 839lux
2 : 1.7klux
3 : 3.3klux
4 : 6.7klux
5 : 13.4klux
6 : 26.7klux
7 : 53.7klux
8 : 107klux
12 : Auto-Range
9-6CONVERSION_TIMER/W8hControls the device conversion time
0 : 600µs
1 : 1ms
2 : 1.8ms
3 : 3.4ms
4 : 6.5ms
5 : 12.7ms
6 : 25ms
7 : 50ms
8 : 100ms
9 : 200ms
10 : 400ms
11 : 800ms
5-4OPERATING_MODER/W0hControls device mode of operation
0 : Power-down
1 : Forced auto-range One-shot
2 : One-shot
3 : Continuous
3-3LATCHR/W1hControls the functionality of the interrupt reporting mechanisms for INT pin (USON variant only)

for the threshold detection logic.

2-2INT_POLR/W0hControls the polarity or active state of the INT pin (USON variant only).
0 : Active Low
1 : Active High
1-0FAULT_COUNTR/W0hFault count register instructs the device as to how many consecutive fault events are required to trigger the threshold mechanisms: the flag high (FLAG_H) and the flag low (FLAG_L) registers.
0 : One fault Count
1 : Two Fault Counts
2 : Four Fault Counts
3 : Eight Fault Counts

7.1.12 Register Bh (offset = Bh) [reset = 8011h]

Figure 7-24 Register Bh
15141312111098
10000000
R/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
000INT_DIRINT_CFG0I2C_BURST
R/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-25 Register 0B Field Descriptions
BitFieldTypeResetDescription
15-51024R/W400hMust read or write 1024
4-4INT_DIRR/W1hDetermines the direction of the INT pin (USON variant only).
0 : Input
1 : Output
3-2INT_CFGR/W0hControls the output interrupt mechanism after end of conversion (USON variant only).
0 : SMBUS Alert
1 : INT Pin asserted after every conversion
2: Invalid
3: INT pin asserted after every 4 conversions (FIFO full)
1-10R/W0hMust read or write 0
0-0I2C_BURSTR/W1hWhen set, enables I2C burst mode minimizing I2C read cycles by auto incrementing read register pointer by 1 after every register read

7.1.13 Register Ch (offset = Ch) [reset = 0h]

Figure 7-26 Register Ch
15141312111098
00000000
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
0000OVERLOAD_FLAGCONVERSION_READY_FLAGFLAG_HFLAG_L
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-27 Register 0C Field Descriptions
BitFieldTypeResetDescription
15-40R/W0hMust read or write 0
3-3OVERLOAD_FLAGR0hIndicates when an overflow condition occurs in the data conversion process, typically because the light illuminating the device exceeds the full-scale range.
2-2CONVERSION_READY_FLAGR0hConversion ready flag indicates when a conversion completes. The flag is set to 1 at the end of a conversion and is cleared (set to 0) when register address 0xC is either read or written with any non-zero value
0 : Conversion in progress
1 : Conversion is complete
1-1FLAG_HR0hFlag high register identifies that the result of a conversion is measurement than a specified level of interest. FLAG_H is set to 1 when the result is larger than the level in the THRESHOLD_H_EXPONENT and THRESHOLD_H_RESULT registers for a consecutive number of measurements defined by the FAULT_COUNT register.

0-0FLAG_LR0hFlag low register identifies that the result of a measurement is smaller than a specified level of interest. FL is set to 1 when the result is smaller than the level in the THRESHOLD_LOW_EXPONENT and THRESHOLD_L_RESULT registers for a consecutive number of measurements defined by the FAULT_COUNT register.

7.1.14 Register 11h (offset = 11h) [reset = 121h]

Figure 7-28 Register 11h
15141312111098
00DIDLDIDH
R/W-0hR/W-0hR-0hR-1h
76543210
DIDH
R-21h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-29 Register 11 Field Descriptions
BitFieldTypeResetDescription
15-140R/W0hMust read or write 0
13-12DIDLR0hDevice ID L
11-0DIDHR121hDevice ID H