SBASA67 June   2023 OPT4060

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Infrared Light Rejection
      2. 8.3.2 Automatic Full-Scale Range Setting
      3. 8.3.3 Output Register CRC and Counter
        1. 8.3.3.1 Output Sample Counter
        2. 8.3.3.2 Output CRC
        3. 8.3.3.3 Threshold Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
      2. 8.4.2 Interrupt Modes of Operation
      3. 8.4.3 Light Range Selection
      4. 8.4.4 Selecting Conversion Time
      5. 8.4.5 Light and Color Measurement
        1. 8.4.5.1 Determining ADC Codes for Each Channel
        2. 8.4.5.2 Lux and Color Calculations
        3. 8.4.5.3 Threshold Detection Calculations
      6. 8.4.6 Light Resolution
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Overview
        1. 8.5.1.1 Serial Bus Address
        2. 8.5.1.2 Serial Interface
      2. 8.5.2 Writing and Reading
        1. 8.5.2.1 High-Speed I2C Mode
        2. 8.5.2.2 Burst Read Mode
        3. 8.5.2.3 General-Call Reset Command
        4. 8.5.2.4 SMBus Alert Response
    6. 8.6 Register Maps
      1. 8.6.1 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Electrical Interface
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Optical Interface
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Optomechanical Design
        3. 9.2.1.3 Application Curve
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Soldering and Handling Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 Register Map

8.6.1.1 Register 0h (offset = 0h) [reset = 0h]

Figure 8-9 Register 0h
15 14 13 12 11 10 9 8
EXPONENT_CH0 RESULT_MSB_CH0
R-0h R-0h
7 6 5 4 3 2 1 0
RESULT_MSB_CH0
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-10 Register 00 Field Descriptions
Bit Field Type Reset Description
15-12 EXPONENT_CH0 R 0h EXPONENT output CH0. Determines the full-scale range of the light measurement for the channel.
11-0 RESULT_MSB_CH0 R 0h Result register MSB (Most significant bits) CH0. Used to calculate the MANTISSA representing light level within a given EXPONENT or full-scale range

8.6.1.2 Register 1h (offset = 1h) [reset = 0h]

Figure 8-11 Register 1h
15 14 13 12 11 10 9 8
RESULT_LSB_CH0
R-0h
7 6 5 4 3 2 1 0
COUNTER_CH0 CRC_CH0
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-12 Register 01 Field Descriptions
Bit Field Type Reset Description
15-8 RESULT_LSB_CH0 R 0h Result register LSB(Least significant bits) CH0. Used to calculate MANTISSA representing light level within a given EXPONENT or full-scale range
7-4 COUNTER_CH0 R 0h Sample counter CH0. Rolling counter which increments for every conversion
3-0 CRC_CH0 R 0h CRC bits CH0.
R[19:0]=(RESULT_MSB_CH0[11:0]<<8)+RESULT_LSB_CH0[7:0]
X[0]=XOR(EXPONENT_CH0[3:0],R[19:0],CRC_CH0[3:0]) XOR of all bits
X[1]=XOR(CRC_CH0[1],CRC_CH0[3],R[1],R[3],R[5],R[7],R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])
X[2]=XOR(CRC_CH0[3],R[3],R[7],R[11],R[15],R[19],E[3])
X[3]=XOR(R[3],R[11],R[19])

8.6.1.3 Register 2h (offset = 2h) [reset = 0h]

Figure 8-13 Register 2h
15 14 13 12 11 10 9 8
EXPONENT_CH1 RESULT_MSB_CH1
R-0h R-0h
7 6 5 4 3 2 1 0
RESULT_MSB_CH1
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-14 Register 02 Field Descriptions
Bit Field Type Reset Description
15-12 EXPONENT_CH1 R 0h EXPONENT output CH1. Determines the full-scale range of the light measurement for the channel.
11-0 RESULT_MSB_CH1 R 0h Result register MSB (Most significant bits) CH1. Used to calculate the MANTISSA representing light level within a given EXPONENT or full-scale range

8.6.1.4 Register 3h (offset = 3h) [reset = 0h]

Figure 8-15 Register 3h
15 14 13 12 11 10 9 8
RESULT_LSB_CH1
R-0h
7 6 5 4 3 2 1 0
COUNTER_CH1 CRC_CH1
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-16 Register 03 Field Descriptions
Bit Field Type Reset Description
15-8 RESULT_LSB_CH1 R 0h Result register LSB(Least significant bits) CH1. Used to calculate MANTISSA representing light level within a given EXPONENT or full-scale range
7-4 COUNTER_CH1 R 0h Sample counter CH1. Rolling counter which increments for every conversion
3-0 CRC_CH1 R 0h CRC bits CH1.
R[19:0]=(RESULT_MSB_CH1[11:0] <<8)+RESULT_LSB_CH1[7:0]
X[0]=XOR(EXPONENT_CH1[3:0],R[19:0],CRC_CH1[3:0]) XOR of all bits
X[1]=XOR(CRC_CH1[1],CRC_CH1[3],R[1],R[3],R[5],R[7],R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])
X[2]=XOR(CRC_CH1[3],R[3],R[7],R[11],R[15],R[19],E[3])
X[3]=XOR(R[3],R[11],R[19])

8.6.1.5 Register 4h (offset = 4h) [reset = 0h]

Figure 8-17 Register 4h
15 14 13 12 11 10 9 8
EXPONENT_CH2 RESULT_MSB_CH2
R-0h R-0h
7 6 5 4 3 2 1 0
RESULT_MSB_CH2
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-18 Register 04 Field Descriptions
Bit Field Type Reset Description
15-12 EXPONENT_CH2 R 0h EXPONENT output CH2. Determines the full-scale range of the light measurement for the channel.
11-0 RESULT_MSB_CH2 R 0h Result register MSB (Most significant bits) CH2. Used to calculate the MANTISSA representing light level within a given EXPONENT or full-scale range

8.6.1.6 Register 5h (offset = 5h) [reset = 0h]

Figure 8-19 Register 5h
15 14 13 12 11 10 9 8
RESULT_LSB_CH2
R-0h
7 6 5 4 3 2 1 0
COUNTER_CH2 CRC_CH2
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-20 Register 05 Field Descriptions
Bit Field Type Reset Description
15-8 RESULT_LSB_CH2 R 0h Result register LSB(Least significant bits) CH2. Used to calculate MANTISSA representing light level within a given EXPONENT or full-scale range
7-4 COUNTER_CH2 R 0h Sample counter CH2. Rolling counter which increments for every conversion
3-0 CRC_CH2 R 0h CRC bits CH2.
R[19:0]=(RESULT_MSB_CH2[11:0]<<8)+RESULT_LSB_CH2[7:0]
X[0]=XOR(EXPONENT_CH2[3:0],R[19:0],CRC_CH2[3:0]) XOR of all bits
X[1]=XOR(CRC_CH2[1],CRC_CH2[3],R[1],R[3],R[5],R[7],R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])
X[2]=XOR(CRC_CH2[3],R[3],R[7],R[11],R[15],R[19],E[3])
X[3]=XOR(R[3],R[11],R[19])

8.6.1.7 Register 6h (offset = 6h) [reset = 0h]

Figure 8-21 Register 6h
15 14 13 12 11 10 9 8
EXPONENT_CH3 RESULT_MSB_CH3
R-0h R-0h
7 6 5 4 3 2 1 0
RESULT_MSB_CH3
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-22 Register 06 Field Descriptions
Bit Field Type Reset Description
15-12 EXPONENT_CH3 R 0h EXPONENT output CH3. Determines the full-scale range of the light measurement for the channel.
11-0 RESULT_MSB_CH3 R 0h Result register MSB (Most significant bits) CH3. Used to calculate the MANTISSA representing light level within a given EXPONENT or full-scale range

8.6.1.8 Register 7h (offset = 7h) [reset = 0h]

Figure 8-23 Register 7h
15 14 13 12 11 10 9 8
RESULT_LSB_CH3
R-0h
7 6 5 4 3 2 1 0
COUNTER_CH3 CRC_CH3
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-24 Register 07 Field Descriptions
Bit Field Type Reset Description
15-8 RESULT_LSB_CH3 R 0h Result register LSB(Least significant bits) CH3. Used to calculate MANTISSA representing light level within a given EXPONENT or full-scale range
7-4 COUNTER_CH3 R 0h Sample counter CH3. Rolling counter which increments for every conversion
3-0 CRC_CH3 R 0h CRC bits CH3.
R[19:0]=(RESULT_MSB_CH3[11:0]<<8)+RESULT_LSB_CH3[7:0]
X[0]=XOR(EXPONENT_CH3[3:0],R[19:0],CRC_CH3[3:0]) XOR of all bits
X[1]=XOR(CRC_CH3[1],CRC_CH3[3],R[1],R[3],R[5],R[7],R[9],R[11],R[13],R[15],R[17],R[19],E[1],E[3])
X[2]=XOR(CRC_CH3[3],R[3],R[7],R[11],R[15],R[19],E[3])
X[3]=XOR(R[3],R[11],R[19])

8.6.1.9 Register 8h (offset = 8h) [reset = 0h]

Figure 8-25 Register 8h
15 14 13 12 11 10 9 8
THRESHOLD_L_EXPONENT THRESHOLD_L_RESULT
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
THRESHOLD_L_RESULT
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-26 Register 08 Field Descriptions
Bit Field Type Reset Description
15-12 THRESHOLD_L_EXPONENT R/W 0h Threshold low register exponent
11-0 THRESHOLD_L_RESULT R/W 0h Threshold low register result

8.6.1.10 Register 9h (offset = 9h) [reset = BFFFh]

Figure 8-27 Register 9h
15 14 13 12 11 10 9 8
THRESHOLD_H_EXPONENT THRESHOLD_H_RESULT
R/W-Bh R/W-Fh
7 6 5 4 3 2 1 0
THRESHOLD_H_RESULT
R/W-FFh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-28 Register 09 Field Descriptions
Bit Field Type Reset Description
15-12 THRESHOLD_H_EXPONENT R/W Bh Threshold high register exponent
11-0 THRESHOLD_H_RESULT R/W FFFh Threshold high register result

8.6.1.11 Register Ah (offset = Ah) [reset = 3208h]

Figure 8-29 Register Ah
15 14 13 12 11 10 9 8
QWAKE 0 RANGE CONVERSION_TIME
R/W-0h W-0h R/W-Ch R/W-2h
7 6 5 4 3 2 1 0
CONVERSION_TIME OPERATING_MODE LATCH INT_POL FAULT_COUNT
R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-30 Register 0A Field Descriptions
Bit Field Type Reset Description
15-15 QWAKE R/W 0h Quick Wake-up from Standby in one shot mode by not powering down all circuits. Applicable only in one shot mode and helps get out of standby mode faster with penalty in power consumption compared to full standby mode.
14-14 0 W 0h Must read or write 0
13-10 RANGE R/W Ch Controls the full-scale light level range of the device. The format of this register is same as the EXPONENT register for all values from 0 to 6.
0 : 2.2klux
1 : 4.5kux
2 : 9klux
3 : 18klux
4 : 36klux
5 : 72klux
6 : 144klux
12 : Auto-Range
9-6 CONVERSION_TIME R/W 8h Controls the device conversion time per channel
0 : 600 us
1 : 1 ms
2 : 1.8 ms
3 : 3.4 ms
4 : 6.5 ms
5 : 12.7 ms
6 : 25 ms
7 : 50 ms
8 : 100 ms
9 : 200 ms
10 : 400 ms
11 : 800 ms
5-4 OPERATING_MODE R/W 0h Controls device mode of operation
0 : Power-down
1 : Forced auto-range OneShot
2 : OneShot
3 : Continuous
3-3 LATCH R/W 1h Controls the functionality of the interrupt reporting mechanisms for INT pin for the threshold detection logic.
2-2 INT_POL R/W 0h Controls the polarity or active state of the INT pin.
0 : Active Low
1 : Active High
1-0 FAULT_COUNT R/W 0h Fault count register instructs the device as to how many consecutive fault events are required to trigger the threshold mechanisms: the flag high (FLAG_H) and the flag low (FLAG_L) registers.
0 : One fault Count
1 : Two Fault Counts
2 : Four Fault Counts
3 : Eight Fault Counts

8.6.1.12 Register Bh (offset = Bh) [reset = 8011h]

Figure 8-31 Register Bh
15 14 13 12 11 10 9 8
1 0 0 0 0 0 0 0
R/W-1h R/W-0h W-0h W-0h W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 THRESHOLD_CH_SEL INT_DIR INT_CFG 0 I2C_BURST
R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-32 Register 0B Field Descriptions
Bit Field Type Reset Description
15-7 128 R/W 80h Must read or write 128
6-5 THRESHOLD_CH_SEL R/W 0h Channel select for threshold logic
0 : CH0 Selected
1 : CH1 Selected
2 : CH2 Selected
3 : CH3 Selected
4-4 INT_DIR R/W 1h Determines the direction of the INT pin.
0 : Input
1 : Output
3-2 INT_CFG R/W 0h Controls the output interrupt mechanism after end of conversion
0 : SMBUS Alert
1 : INT Pin data ready for next channel
3 : INT Pin data ready for all channels
1-1 0 R/W 0h Must read or write 0
0-0 I2C_BURST R/W 1h When set enables I2C burst mode minimizing I2C read cycles by auto incrementing read register point by 1 after every register read

8.6.1.13 Register Ch (offset = Ch) [reset = 0h]

Figure 8-33 Register Ch
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 OVERLOAD_FLAG CONVERSION_READY_FLAG FLAG_H FLAG_L
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-34 Register 0C Field Descriptions
Bit Field Type Reset Description
15-4 0 R/W 0h Must read or write 0
3-3 OVERLOAD_FLAG R 0h Indicates when an overflow condition occurs in the data conversion process, typically because the light illuminating the device exceeds the full-scale range.
2-2 CONVERSION_READY_FLAG R 0h Conversion ready flag indicates when a conversion completes. The flag is set to 1 at the end of a conversion and is cleared (set to 0) when register address 0xA is either read or written with any non-zero value
0 : Conversion in progress
1 : Conversion is complete
1-1 FLAG_H R 0h Flag high register identifies that the result of a conversion is measurement than a specified level of interest. FLAG_H is set to 1 when the result is larger than the level in the THRESHOLD_H_EXPONENT and THRESHOLD_H_RESULT registers for a consecutive number of measurements defined by the FAULT_COUNT register.
0-0 FLAG_L R 0h Flag low register identifies that the result of a measurement is smaller than a specified level of interest. FLAG_L is set to 1 when the result is smaller than the level in the THRESHOLD_L_EXPONENT and THRESHOLD_L_RESULT registers for a consecutive number of measurements defined by the FAULT_COUNT register.

8.6.1.14 Register 11h (offset = 11h) [reset = 820h]

Figure 8-35 Register 11h
15 14 13 12 11 10 9 8
0 0 DIDL DIDH
R/W-0h R/W-0h R-0h R-8h
7 6 5 4 3 2 1 0
DIDH
R-21h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 8-36 Register 11 Field Descriptions
Bit Field Type Reset Description
15-14 0 R/W 0h Must read or write 0
13-12 DIDL R 8h Device ID L
11-0 DIDH R 21h Device ID H