P82B96 I2C Compatible Dual Bidirectional Bus Buffer
- SCPS144C May 2006 – May 2015 P82B96
  
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DATA SHEET

P82B96 I2C Compatible Dual Bidirectional Bus Buffer

1 Features

Operating Power-Supply Voltage Range of 2 V to 15 V
Can Interface Between I²C Buses Operating at Different Logic Levels (2 V to 15 V)
Longer Cables by allowing bus capacitance of 400 pF on Main Side (Sx/Sy) and 4000 pF on Transmission Side (Tx/Ty)
Outputs on the Transmission Side (Tx/Ty) Have High Current Sink Capability for Driving Low-Impedance or High-Capacitive Buses
Interface With Optoelectrical Isolators and Similar Devices That Need Unidirectional Input and Output Signal Paths by Splitting I²C Bus Signals Into Pairs of Forward (Tx/Ty) and Reverse (Rx/Ry) Signals
400-kHz Fast I²C Bus Operation Over at Least 20 Meters of Wire
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22

2 Applications

HDMI DDC
Long I²C Communication
Galvanic I²C Isolation
Industrial Communications

3 Description

The P82B96 device is a bus buffer that supports bidirectional data transfer between an I²C bus and a range of other bus configurations with different voltage and current levels.

One of the advantages of the P82B96 is that it supports longer cables/traces and allows for more devices per I²C bus because it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote I²C nodes are not apparent to other I²C buses (or nodes). The restrictions on the number of I²C devices in a system due to capacitance, or the physical separation between them, are greatly improved.

The device is able to provide galvanic isolation (optocoupling) or use balanced transmission lines (twisted pairs), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected directly (without causing bus latching), to provide an bidirectional signal line with I²C properties (open-drain driver). Likewise, the Ty and Ry signals may also be connected together to provide an bidirectional signal line with I²C properties (open-drain driver). This allows for a simple communication design, saving design time and costs.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
P82B96	SOIC (8)	4.90 mm × 3.91 mm
	VSSOP (8)	3.00 mm × 3.00 mm
	PDIP (8)	9.81 mm × 6.35 mm
	TSSOP (8)	3.00 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Long-Distance I²C Communications

4 Revision History

Changes from B Revision (July 2007) to C Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
Changed V_CC pins to VCC pins in pinout diagramsGo

5 Description (continued)

Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does not support this configuration. Bidirectional I²C signals do not have a direction control pin so, instead, slightly different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I²C low applied at the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard I²C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation.

The Sx/Sy side of the P82B96 is intended for I²C logic voltage levels of I²C master and slave devices or Tx/Rx signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.

In any design, the Sx pins of different devices should never be linked, because the resulting system would be very susceptible to induced noise and would not support all I²C operating modes.

6 Pin Configuration and Functions

P Package

8-Pin PDIP

(Top View)

PW Package

8-Pin TSSOP

(Top View)

D Package

8-Pin SOIC

(Top View)

DGK Package

8-Pin VSSOP

(Top View)

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	Sx	I/O	Serial data bus or SDA. Connect to V_CC of I²C master through a pullup resistor.
2	Rx	I	Receive signal. Connect to V_CC of P82B96 through a pullup resistor.
3	Tx	O	Transmit signal. Connect to V_CC of P82B96 through a pullup resistor.
4	GND	—	Ground
5	Ty	O	Transmit signal. Connect to V_CC of P82B96 through a pullup resistor.
6	Ry	I	Receive signal. Connect to V_CC of P82B96 through a pullup resistor.
7	Sy	I/O	Serial clock bus or SCL. Connect to V_CC of I²C master through a pullup resistor.
8	VCC	I	Supply voltage

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage on VCC pin		–0.3	18	V
V_I	Voltage on buffered input	Sx or Sy (SDA or SCL)	–0.3	18	V
V_I	Voltage on buffered input	Rx or Ry	–0.3	18	V
V_O	Voltage on buffered output	Sx or Sy (SDA or SCL)	–0.3	18	V
V_O	Voltage on buffered output	Tx or Ty	–0.3	18	V
I_O	Continuous output current	Sx or Sy		250	mA
I_O	Continuous output current	Tx or Ty		250	mA
I_CC	Continuous current through VCC or GND			250	mA
T_A	Operating free-air temperature		–40	85	°C
T_stg	Storage temperature		–55	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±3500	V
		Charged-Device Model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		Machine Model (MM), per JEDEC specification JESD22-A115-A	±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

				MIN	MAX	UNIT
V_CC	Supply voltage			2	15	V
I_OL	Low-level output current	Sx, Sy	V_Sx, V_Sy = 1 V, V_Rx, V_Ry ≤ 0.42 V		3	mA
I_OL	Low-level output current	Tx, Ty	V_Sx, V_Sy = 0.4 V, V_Tx, V_Ty = 0.4 V		30	mA
V_IOmax	Maximum input/output voltage level	Sx, Sy	V_Tx, V_Ty = 0.4 V		15	V
V_IOmax	Maximum input/output voltage level	Tx, Ty	V_Sx, V_Sy = 0.4 V		15	V
V_ILdiff	Low-level input voltage difference	Sx, Sy			0.4	V
T_A	Operating free-air temperature			–40	85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		P82B96				UNIT
		D (SOIC)	DGK (VSSOP)	P (PDIP)	PW (TSSOP)
		8 PINS	8 PINS	8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	109.1	174.3	53.5	173.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	61.6	63	44.4	57.6	°C/W
R_θJB	Junction-to-board thermal resistance	48.6	94.2	30.6	101.8	°C/W
ψ_JT	Junction-to-top characterization parameter	19.6	8.1	22.9	5.3	°C/W
ψ_JB	Junction-to-board characterization parameter	48.2	92.8	30.5	100.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: V_CC = 2.3 V to 2.7 V

V_CC = 2.3 V to 2.7 V, voltages are specified with respect to GND (unless otherwise noted)

PARAMETER			TEST CONDITIONS	T_A= 25°C			T_A= –40°C to 85°C		UNIT
PARAMETER			TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	MIN	MAX	UNIT
ΔV/ΔT_IN	Temperature coefficient of input thresholds	Sx, Sy			–2				mV/°C
V_OL	Low-level output voltage	Sx, Sy	I_Sx, I_Sy = 3 mA	0.8	0.88	1	See ⁽²⁾		V
V_OL	Low-level output voltage	Sx, Sy	I_Sx, I_Sy = 0.2 mA	0.67	0.73	0.79	See ⁽²⁾		V
ΔV/ΔT_OUT	Temperature coefficient of output low levels⁽³⁾	Sx, Sy	I_Sx, I_Sy = 0.2 mA		–1.8				mV/°C
I_CC	Quiescent supply current		Sx = Sy = V_CC		0.9	1.8		2	mA
ΔI_CC	Additional supply current per pin low	Tx, Ty			1.7	2.75		3	mA
I_IOS	Dynamic output sink capability on I²C bus	Sx, Sy	V_Sx, V_Sy > 2 V, V_Rx, V_Ry = low	7	18		5.5		mA
I_IOS	Leakage current on I²C bus	Sx, Sy	V_Sx, V_Sy = 2.5 V, V_Rx, V_Ry = high		0.1	1		1	μA
I_IOT	Dynamic output sink capability on buffered bus	Tx, Ty	V_Tx, V_Ty > 1 V, V_Sx, V_Sy = low on I²C bus = 0.4 V	60	100		60		mA
I_IOT	Leakage current on buffered bus		V_Tx, V_Ty = V_CC = 2.5 V, V_Sx, V_Sy = high		0.1	1		1	μA
I_I	Input current from I²C bus	Sx, Sy	Bus low, V_Rx, V_Ry = high		–1			1	μA
	Input current from buffered bus	Rx, Ry	Bus low, V_Rx, V_Ry = 0.4 V		–1			1
	Leakage current on buffered bus input	Rx, Ry	V_Rx, V_Ry = V_CC		1			1.5
V_IT	Input threshold	Sx, Sy	Input logic level high threshold⁽⁴⁾ on normal I²C bus		0.65	0.7	See ⁽²⁾		V
		Sx, Sy	Input logic level low threshold⁽⁴⁾ on normal I²C bus	0.6	0.65		See ⁽²⁾
		Rx, Ry	Input logic level high	0.58 x V_CC			0.58 x V_CC
			Input threshold		0.5 x V_CC
			Input logic level low			0.42 x V_CC		0.42 x V_CC
V_IOdiff	Input/output logic level difference⁽⁵⁾	Sx, Sy	(V_Sx output low at 3 mA) – (V_Sx input high max) for I²C applications	100	150		100		mV
V_IOrel	V_CC voltage at which all buses are released	Sx, Sy Tx, Ty	Sx, Sy are low, V_CC ramping, voltage on Tx, Ty lowered until released	1			1		V
ΔV/ΔT_REL	Temperature coefficient of release voltage				–4				mV/°C
C_in	Input capacitance	Rx, Ry			2.5	4		4	pF

(1) Typical value is at V_CC = 2.5 V, T_A = 25°C

(2) See the Typical Characteristics section of this data sheet.

(3) The output logic low depends on the sink current.

(4) The input logic threshold is independent of the supply voltage.

(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V_SX output low always exceeds the minimum V_Sx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device. While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications.

7.6 Electrical Characteristics: V_CC = 3 V to 3.6 V

V_CC = 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)

PARAMETER			TEST CONDITIONS	T_A= 25°C			T_A= –40°C to 85°C		UNIT
PARAMETER			TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	MIN	MAX	UNIT
ΔV/ΔT_IN	Temperature coefficient of input thresholds	Sx, Sy			–2				mV/°C
V_OL	Low-level output voltage	Sx, Sy	I_Sx, I_Sy = 3 mA	0.8	0.88	1	See ⁽²⁾		V
V_OL	Low-level output voltage	Sx, Sy	I_Sx, I_Sy = 0.2 mA	0.67	0.73	0.79	See ⁽²⁾		V
ΔV/ΔT_OUT	Temperature coefficient of output low levels⁽³⁾	Sx, Sy	I_Sx, I_Sy = 0.2 mA		–1.8				mV/°C
I_CC	Quiescent supply current		Sx = Sy = V_CC		0.9	1.8		2	mA
ΔI_CC	Additional supply current per pin low	Tx, Ty			1.7	2.75		3	mA
I_IOS	Dynamic output sink capability on I²C bus	Sx, Sy	V_Sx, V_Sy > 2 V, V_Rx, V_Ry = low	7	18		5.7		mA
I_IOS	Leakage current on I²C bus	Sx, Sy	V_Sx, V_Sy = 5 V, V_Rx, V_Ry = high		0.1	1		1	μA
I_IOT	Dynamic output sink capability on buffered bus	Tx, Ty	V_Tx, V_Ty > 1 V, V_Sx, V_Sy = low on I²C bus = 0.4 V	60	100		60		mA
I_IOT	Leakage current on buffered bus	Tx, Ty	V_Tx, V_Ty = V_CC = 3.3 V, V_Sx, V_Sy = high		0.1	1		1	μA
I_I	Input current from I²C bus	Sx, Sy	Bus low, V_Rx, V_Ry = high		–1			1	μA
	Input current from buffered bus	Rx, Ry	Bus low, V_Rx, V_Ry = 0.4 V		–1			1
	Leakage current on buffered bus input	Rx, Ry	V_Rx, V_Ry = V_CC		1			1.5
V_IT	Input threshold	Sx, Sy	Input logic-level high threshold⁽⁴⁾ on normal I²C bus		0.65	0.7	See ⁽²⁾		V
		Sx, Sy	Input logic-level low threshold⁽⁴⁾ on normal I²C bus	0.6	0.65		See ⁽²⁾
		Rx, Ry	Input logic level high	0.58 x V_CC			0.58 x V_CC
			Input threshold		0.5 x V_CC
			Input logic level low			0.42 x V_CC		0.42 x V_CC
V_IOdiff	Input/output logic level difference⁽⁴⁾	Sx, Sy	(V_Sx output low at 3 mA) – (V_Sx input high max) for I²C applications	100	150		100		mV
V_IOrel	V_CC voltage at which all buses are released	Sx, Sy Tx, Ty	Sx, Sy are low, V_CC ramping, voltage on Tx, Ty lowered until released	1			1		V
ΔV/ΔT_REL	Temperature coefficient of release voltage				–4				mV/°C
C_in	Input capacitance	Rx, Ry			2.5	4		4	pF

(1) Typical value is at V_CC = 3.3 V, T_A = 25°C

(2) See the Typical Characteristics section of this data sheet.

(3) The output logic low depends on the sink current.

(4) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V_SX output low always exceeds the minimum V_Sx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device. While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications.

7.7 Electrical Characteristics: V_CC = 4.5 V to 5.5 V

V_CC = 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)

PARAMETER			TEST CONDITIONS	T_A= 25°C			T_A= –40°C to 85°C		UNIT
PARAMETER			TEST CONDITIONS	MIN	TYP⁽⁴⁾	MAX	MIN	MAX	UNIT
ΔV/ΔT_IN	Temperature coefficient of input thresholds	Sx, Sy			–2				mV/°C
V_OL	Low-level output voltage	Sx, Sy	I_Sx, I_Sy = 3 mA	0.8	0.88	1	See ⁽⁵⁾		V
V_OL	Low-level output voltage	Sx, Sy	I_Sx, I_Sy = 0.2 mA	0.67	0.73	0.79	See ⁽⁵⁾		V
ΔV/ΔT_OUT	Temperature coefficient of output low levels⁽²⁾	Sx, Sy	I_Sx, I_Sy = 0.2 mA		–1.8				mV/°C
I_CC	Quiescent supply current		Sx = Sy = V_CC		0.9	1.8		2	mA
ΔI_CC	Additional supply current per pin low	Tx, Ty			1.7	2.75		3	mA
I_IOS	Dynamic output sink capability on I²C bus	Sx, Sy	V_Sx, V_Sy > 2 V, V_Rx, V_Ry = low	7	18		6		mA
I_IOS	Leakage current on I²C bus	Sx, Sy	V_Sx, V_Sy = 5 V, V_Rx, V_Ry = high		0.1	1		1	μA
I_IOT	Dynamic output sink capability on buffered bus	Tx, Ty	V_Tx, V_Ty > 1 V, V_Sx, V_Sy = low on I²C bus = 0.4 V	60	100		60		mA
I_IOT	Leakage current on buffered bus	Tx, Ty	V_Tx, V_Ty = V_CC = 5 V, V_Sx, V_Sy = high		0.1	1		1	μA
I_I	Input current from I²C bus	Sx, Sy	Bus low, V_Rx, V_Ry = high		–1			1	μA
	Input current from buffered bus	Rx, Ry	Bus low, V_Rx, V_Ry = 0.4 V		–1			1
	Leakage current on buffered bus input	Rx, Ry	V_Rx, V_Ry = V_CC		1			1.5
V_IT	Input threshold	Sx, Sy	Input logic-level high threshold⁽³⁾ on normal I²C bus		0.65	0.7	See ⁽⁵⁾		V
		Sx, Sy	Input logic-level low threshold⁽³⁾ on normal I²C bus	0.6	0.65		See ⁽⁵⁾
		Rx, Ry	Input logic level high	0.58 x V_CC			0.58 x V_CC
			Input threshold		0.5 x V_CC
			Input logic level low			0.42 x V_CC		0.42 x V_CC
V_IOdiff	Input/output logic level difference⁽¹⁾	Sx, Sy	(V_Sx output low at 3 mA) – (V_Sx input high max) for I²C applications	100	150		100		mV
V_IOrel	V_CC voltage at which all buses are released	Sx, Sy Tx, Ty	Sx, Sy are low, V_CC ramping, voltage on Tx, Ty lowered until released	1			1		V
ΔV/ΔT_REL	Temperature coefficient of release voltage				–4				mV/°C
C_in	Input capacitance	Rx, Ry			2.5	4		4	pF

(1) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V_SX output low always exceeds the minimum V_Sx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device. While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications.

(2) The output logic low depends on the sink current.

(3) The input logic threshold is independent of the supply voltage.

(4) Typical value is at V_CC = 5 V, T_A = 25°C

(5) See the Typical Characteristics section of this data sheet.

7.8 Electrical Characteristics: V_CC = 15 V

V_CC = 15 V, voltages are specified with respect to GND (unless otherwise noted)

PARAMETER			TEST CONDITIONS	T_A= 25°C			T_A= –40°C to 85°C		UNIT
PARAMETER			TEST CONDITIONS	MIN	TYP⁽⁴⁾	MAX	MIN	MAX	UNIT
ΔV/ΔT_IN	Temperature coefficient of input thresholds	Sx, Sy			–2				mV/°C
V_OL	Low-level output voltage	Sx, Sy	I_Sx, I_Sy = 3 mA	0.8	0.88	1	See ⁽⁵⁾		V
V_OL	Low-level output voltage	Sx, Sy	I_Sx, I_Sy = 0.2 mA	0.67	0.73	0.79	See ⁽⁵⁾		V
ΔV/ΔT_OUT	Temperature coefficient of output low levels⁽²⁾	Sx, Sy	I_Sx, I_Sy = 0.2 mA		–1.8				mV/°C
I_CC	Quiescent supply current		Sx = Sy = V_CC		0.9	1.8		2	mA
ΔI_CC	Additional supply current per pin low	Tx, Ty			1.7	2.75		3	mA
I_IOS	Dynamic output sink capability on I²C bus	Sx, Sy	V_Sx, V_Sy > 2 V, V_Rx, V_Ry = low	7	18		6.5		mA
I_IOS	Leakage current on I²C bus	Sx, Sy	V_Sx, V_Sy = 15 V, V_Rx, V_Ry = high		0.1	1		1	μA
I_IOT	Dynamic output sink capability on buffered bus	Tx, Ty	V_Tx, V_Ty > 1 V, V_Sx, V_Sy = low on I²C bus = 0.4 V	60	100		60		mA
I_IOT	Leakage current on buffered bus	Tx, Ty	V_Tx, V_Ty = V_CC = 15 V, V_Sx, V_Sy = high		0.1	1		1	μA
I_I	Input current from I²C bus	Sx, Sy	Bus low, V_Rx, V_Ry = high		–1			1	μA
	Input current from buffered bus	Rx, Ry	Bus low, V_Rx, V_Ry = 0.4 V		–1			1
	Leakage current on buffered bus input	Rx, Ry	V_Rx, V_Ry = V_CC		1			1.5
V_IT	Input threshold	Sx, Sy	Input logic-level high threshold⁽³⁾ on normal I²C bus		0.65	0.7	See ⁽⁵⁾		V
		Sx, Sy	Input logic-level high threshold⁽³⁾ on normal I²C bus	0.6	0.65		See ⁽⁵⁾
		Rx, Ry	Input logic level high	0.58 x V_CC			0.58 x V_CC
			Input threshold		0.5 x V_CC
			Input logic level low			0.42 x V_CC		0.42 x V_CC
V_IOdiff	Input/output logic level difference⁽¹⁾	Sx, Sy	(V_Sx output low at 3 mA) – (V_Sx input high max) for I²C applications	100	150		100		mV
V_IOrel	V_CC voltage at which all buses are released	Sx, Sy Tx, Ty	Sx, Sy are low, V_CC ramping, voltage on Tx, Ty lowered until released	1			1		V
ΔV/ΔT_REL	Temperature coefficient of release voltage				–4				mV/°C
C_in	Input capacitance	Rx, Ry			2.5	4		4	pF

(2) The output logic low depends on the sink current.

(3) The input logic threshold is independent of the supply voltage.

(4) Typical value is at V_CC = 15 V, T_A = 25°C

(5) See the Typical Characteristics section of this data sheet.

7.9 Switching Characteristics

V_CC = 5 V, T_A = 25°C, no capacitive loads, voltages are specified with respect to GND (unless otherwise noted)

PARAMETER		FROM (INPUT)	TO (OUTPUT)	TEST CONDITIONS	TYP	UNIT
t_pzl	Buffer delay time on falling input	V_Sx (or V_Sy) = input switching threshold	V_Tx (or V_Ty) output falling 50% of V_LOAD⁽¹⁾	R_Tx pullup = 160 Ω, C_Tx = 7 pF + board trace capacitance	70	ns
t_plz	Buffer delay time on rising input	V_Sx (or V_Sy) = input switching threshold	V_Tx (or V_Ty) output reaching 50% of V_LOAD⁽³⁾	R_Tx pullup = 160 Ω, C_Tx = 7 pF + board trace capacitance	90	ns
t_pzl	Buffer delay time on falling input	V_Rx (or V_Ry) = input switching threshold	V_Sx (or V_Sy) output falling 50% of V_LOAD⁽²⁾	R_Sx pullup = 1500 Ω, C_Tx = 7 pF + board trace capacitance	250	ns
t_plz	Buffer delay time on rising input	V_Rx (or V_Ry) = input switching threshold	V_Sx (or V_Sy) output reaching 50% of V_LOAD⁽⁴⁾	R_Sx pullup = 1500 Ω, C_Tx = 7 pF + board trace capacitance	270	ns

(1) The fall time of V_Tx from 5 V to 2.5 V in the test is approximately 15 ns.

(2) The fall time of V_Sx from 5 V to 2.5 V in the test is approximately 50 ns.

(3) The rise time of V_Tx from 0 V to 2.5 V in the test is approximately 20 ns.

(4) The rise time of V_Sx from 0.9 V to 2.5 V in the test is approximately 70 ns.

7.10 Typical Characteristics

Figure 1. V_OL at Sx vs Junction Temperature, I_OL = 0.2 mA

Figure 3. V_IL(max) at Sx vs Junction Temperature

Figure 5. V_CC(max) vs Junction Temperature

Figure 2. V_OL at Sx vs Junction Temperature, I_OL = 3 mA

Figure 4. V_IH(min) at Sx vs Junction Temperature