SCPS113O october   2004  – september 2023 PCA9306

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics AC Performance (Translating Down) (EN = 3.3 V)
    7. 6.7  Switching Characteristics AC Performance (Translating Down) (EN = 2.5 V)
    8. 6.8  Switching Characteristics AC Performance (Translating Up) (EN = 3.3 V)
    9. 6.9  Switching Characteristics AC Performance (Translating Up) (EN = 2.5 V)
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Definition of threshold voltage
      2. 8.1.2 Correct Device Set Up
      3. 8.1.3 Disconnecting an I2C target from the Main I2C Bus Using the EN Pin
      4. 8.1.4 Supporting Remote Board Insertion to Backplane with PCA9306
      5. 8.1.5 Switch Configuration
      6. 8.1.6 Controller on Side 1 or Side 2 of Device
      7. 8.1.7 LDO and PCA9306 Concerns
      8. 8.1.8 Current Limiting Resistance on VREF2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable (EN) Pin
      2. 8.3.2 Voltage Translation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Applications of I2C
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bidirectional Voltage Translation
        2. 9.2.2.2 Sizing Pullup Resistors
        3. 9.2.2.3 PCA9306 Bandwidth
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

For printed-circuit board (PCB) layout of the PCA9306 device, common PCB layout practices should be followed, but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other on leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. The 100-pF filter capacitor should be placed as close to VREF2 as possible. A larger decoupling capacitor can also be used, but a longer time constant of two capacitors and the 200-kΩ resistor results in longer turnon and turnoff times for the PCA9306 device. These best practices are shown in Figure 11-1.

For the layout example provided in Figure 11-1, it would be possible to fabricate a PCB with only two layers by using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However, a four-layer board is preferable for boards with higher-density signal routing. On a four-layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface-mount component pad, which must attach to VCC or GND, and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace must be routed to the opposite side of the board, but this technique is not demonstrated in Figure 11-1.