SCPS141J
September 2006 – March 2021
PCA9534A
PRODUCTION DATA
1
Features
2
Description
3
Revision History
4
Description (Continued)
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Resistance Characteristics
7.5
Electrical Characteristics
7.6
I2C Interface Timing Requirements
7.7
Switching Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Functional Block Diagram
9.2
Device Functional Modes
9.2.1
Power-On Reset
9.2.2
I/O Port
9.2.3
Interrupt Output ( INT)
9.2.3.1
Interrupt Errata
9.2.3.1.1
Description
9.2.3.1.2
System Impact
9.2.3.1.3
System Workaround
9.3
Programming
9.3.1
I2C Interface
9.3.2
Register Map
9.3.2.1
Device Address
9.3.2.2
Control Register And Command Byte
9.3.2.3
Register Descriptions
9.3.2.4
Bus Transactions
9.3.2.4.1
Writes
9.3.2.4.2
Reads
10
Application Information Disclaimer
10.1
Application Information
10.1.1
Typical Application
10.1.1.1
Design Requirements
10.1.1.1.1
Minimizing ICC When The I/O Controls Leds
11
Power Supply Recommendations
11.1
Power-On Reset Requirements
12
Device and Documentation Support
12.1
Trademarks
12.2
Electrostatic Discharge Caution
12.3
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DGV|16
MPDS006C
DW|16
MSOI003I
PW|16
MPDS361A
DB|16
MPDS507A
RGV|16
MPQF121F
RGT|16
MPQF119H
Thermal pad, mechanical data (Package|Pins)
RGV|16
QFND107G
RGT|16
QFND098S
Orderable Information
scps141j_oa
scps141j_pm
1
Features
Low standby current consumption of 1 μA max
I
2
C to Parallel port expander
Open-drain active-low interrupt output
Operating power-supply voltage range of 2.3 V to 5.5 V
5-V Tolerant I/O ports
400-kHz Fast I
2
C bus
Three hardware address pins allow up to eight devices on the I
2
C/SMBus
Allows up to 16 devices on the I
2
C/SMBus when used in conjunction with the
PCA9534
See
Section 5
for I
2
C Expander offerings
Input and output configuration register
Polarity inversion register
Internal power-on reset
Power-up with all channels configured as Inputs
No glitch on power-up
Noise filter on SCL and SDA inputs
Latched outputs with high-current drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA Per JESD 78, Class II
ESD protection exceeds JESD 22
2000-V Human-body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-device model (C101)