SCPS129K
August 2005 – March 2021
PCA9535
PRODUCTION DATA
1
Features
2
Description
3
Revision History
4
Description Continued
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Resistance Characteristics
6.5
Electrical Characteristics
6.6
I2C Interface Timing Requirements
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
16
8
Detailed Description
8.1
Functional Block Diagram
8.2
Device Functional Modes
8.2.1
Power-On Reset
8.2.2
I/O Port
8.2.3
Interrupt ( INT) Output
8.2.3.1
Interrupt Errata
24
25
26
8.3
Programming
8.3.1
I2C Interface
8.3.2
Register Map
8.3.2.1
Device Address
8.3.2.2
Control Register And Command Byte
8.3.2.3
Register Descriptions
8.3.2.4
Bus Transactions
8.3.2.4.1
Writes
8.3.2.4.2
Reads
9
Application Information Disclaimer
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Minimizing ICC When I/O Is Used To Control Led
10
Power Supply Recommendations
10.1
Power-On Reset Requirements
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Support Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DGV|24
MPDS006C
PW|24
MPDS363A
DBQ|24
MPDS211A
RGE|24
MPQF124G
DW|24
MPDS174A
DB|24
MPDS509
RTW|24
MPQF167C
Thermal pad, mechanical data (Package|Pins)
RGE|24
QFND008AA
RTW|24
QFND062N
Orderable Information
scps129k_oa
scps129k_pm
8.1
Functional Block Diagram
Pin numbers shown are for DB, DBQ, DGV, DW, and PW packages.
All I/Os are set to inputs at reset.
Figure 8-1
Logic Diagram (Positive Logic)
At power-on reset, all registers return to default values.
Figure 8-2
Simplified Schematic Of P-Port I/Os